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Merge tag 'drm-next-5.5-2019-11-22' of git://people.freedesktop.org/~agd5f/linux into drm-next
drm-next-5.5-2019-11-22: amdgpu: - Fix bad DMA on some PPC platforms - MMHUB fix for powergating - BACO fix for Navi - Misc raven fixes - Enable vbios fetch directly from rom on navi - debugfs fix for DC - SR-IOV fixes for arcturus - Misc power fixes radeon: - Fix bad DMA on some PPC platforms Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents e639ea0 + f920d1b commit acc61b8

32 files changed

+362
-53
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3109,9 +3109,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
31093109
int r;
31103110

31113111
DRM_INFO("amdgpu: finishing device.\n");
3112-
adev->shutdown = true;
3113-
31143112
flush_delayed_work(&adev->delayed_init_work);
3113+
adev->shutdown = true;
31153114

31163115
/* disable all interrupts */
31173116
amdgpu_irq_disable_all(adev);
@@ -3130,7 +3129,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
31303129
adev->firmware.gpu_info_fw = NULL;
31313130
}
31323131
adev->accel_working = false;
3133-
cancel_delayed_work_sync(&adev->delayed_init_work);
31343132
/* free i2c buses */
31353133
if (!amdgpu_device_has_dc_support(adev))
31363134
amdgpu_i2c_fini(adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -514,7 +514,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
514514
* Also, don't allow GTT domain if the BO doens't have USWC falg set.
515515
*/
516516
if (adev->asic_type >= CHIP_CARRIZO &&
517-
adev->asic_type <= CHIP_RAVEN &&
517+
adev->asic_type < CHIP_RAVEN &&
518518
(adev->flags & AMD_IS_APU) &&
519519
(bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
520520
amdgpu_bo_support_uswc(bo_flags) &&

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -998,10 +998,10 @@ static const struct pci_device_id pciidlist[] = {
998998
{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
999999
{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
10001000
/* Navi14 */
1001-
{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
1002-
{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
1003-
{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
1004-
{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
1001+
{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1002+
{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1003+
{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1004+
{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
10051005

10061006
/* Renoir */
10071007
{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -454,8 +454,6 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
454454
}
455455

456456
ring = &adev->gfx.kiq.ring;
457-
if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring)
458-
kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]);
459457
kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
460458
amdgpu_bo_free_kernel(&ring->mqd_obj,
461459
&ring->mqd_gpu_addr,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,7 @@ struct amdgpu_me {
225225
uint32_t num_me;
226226
uint32_t num_pipe_per_me;
227227
uint32_t num_queue_per_pipe;
228-
void *mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];
228+
void *mqd_backup[AMDGPU_MAX_GFX_RINGS];
229229

230230
/* These are the resources for which amdgpu takes ownership */
231231
DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,7 @@ struct amdgpu_gmc_fault {
7777
struct amdgpu_vmhub {
7878
uint32_t ctx0_ptb_addr_lo32;
7979
uint32_t ctx0_ptb_addr_hi32;
80+
uint32_t vm_inv_eng0_sem;
8081
uint32_t vm_inv_eng0_req;
8182
uint32_t vm_inv_eng0_ack;
8283
uint32_t vm_context0_cntl;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -655,15 +655,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
655655
return -ENOMEM;
656656
alloc_size = info->read_mmr_reg.count * sizeof(*regs);
657657

658-
for (i = 0; i < info->read_mmr_reg.count; i++)
658+
amdgpu_gfx_off_ctrl(adev, false);
659+
for (i = 0; i < info->read_mmr_reg.count; i++) {
659660
if (amdgpu_asic_read_register(adev, se_num, sh_num,
660661
info->read_mmr_reg.dword_offset + i,
661662
&regs[i])) {
662663
DRM_DEBUG_KMS("unallowed offset %#x\n",
663664
info->read_mmr_reg.dword_offset + i);
664665
kfree(regs);
666+
amdgpu_gfx_off_ctrl(adev, true);
665667
return -EFAULT;
666668
}
669+
}
670+
amdgpu_gfx_off_ctrl(adev, true);
667671
n = copy_to_user(out, regs, min(size, alloc_size));
668672
kfree(regs);
669673
return n ? -EFAULT : 0;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

Lines changed: 40 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -758,6 +758,12 @@ static int psp_ras_terminate(struct psp_context *psp)
758758
{
759759
int ret;
760760

761+
/*
762+
* TODO: bypass the terminate in sriov for now
763+
*/
764+
if (amdgpu_sriov_vf(psp->adev))
765+
return 0;
766+
761767
if (!psp->ras.ras_initialized)
762768
return 0;
763769

@@ -779,6 +785,12 @@ static int psp_ras_initialize(struct psp_context *psp)
779785
{
780786
int ret;
781787

788+
/*
789+
* TODO: bypass the initialize in sriov for now
790+
*/
791+
if (amdgpu_sriov_vf(psp->adev))
792+
return 0;
793+
782794
if (!psp->adev->psp.ta_ras_ucode_size ||
783795
!psp->adev->psp.ta_ras_start_addr) {
784796
dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");
@@ -874,6 +886,12 @@ static int psp_hdcp_initialize(struct psp_context *psp)
874886
{
875887
int ret;
876888

889+
/*
890+
* TODO: bypass the initialize in sriov for now
891+
*/
892+
if (amdgpu_sriov_vf(psp->adev))
893+
return 0;
894+
877895
if (!psp->adev->psp.ta_hdcp_ucode_size ||
878896
!psp->adev->psp.ta_hdcp_start_addr) {
879897
dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");
@@ -962,6 +980,12 @@ static int psp_hdcp_terminate(struct psp_context *psp)
962980
{
963981
int ret;
964982

983+
/*
984+
* TODO: bypass the terminate in sriov for now
985+
*/
986+
if (amdgpu_sriov_vf(psp->adev))
987+
return 0;
988+
965989
if (!psp->hdcp_context.hdcp_initialized)
966990
return 0;
967991

@@ -1053,6 +1077,12 @@ static int psp_dtm_initialize(struct psp_context *psp)
10531077
{
10541078
int ret;
10551079

1080+
/*
1081+
* TODO: bypass the initialize in sriov for now
1082+
*/
1083+
if (amdgpu_sriov_vf(psp->adev))
1084+
return 0;
1085+
10561086
if (!psp->adev->psp.ta_dtm_ucode_size ||
10571087
!psp->adev->psp.ta_dtm_start_addr) {
10581088
dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");
@@ -1111,6 +1141,12 @@ static int psp_dtm_terminate(struct psp_context *psp)
11111141
{
11121142
int ret;
11131143

1144+
/*
1145+
* TODO: bypass the terminate in sriov for now
1146+
*/
1147+
if (amdgpu_sriov_vf(psp->adev))
1148+
return 0;
1149+
11141150
if (!psp->dtm_context.dtm_initialized)
11151151
return 0;
11161152

@@ -1431,7 +1467,10 @@ static int psp_np_fw_load(struct psp_context *psp)
14311467
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
14321468
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
14331469
|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1434-
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
1470+
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
1471+
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
1472+
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
1473+
|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM))
14351474
/*skip ucode loading in SRIOV VF */
14361475
continue;
14371476

‎drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -473,7 +473,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
473473
TP_PROTO(struct amdgpu_job *sched_job, struct dma_fence *fence),
474474
TP_ARGS(sched_job, fence),
475475
TP_STRUCT__entry(
476-
__string(ring, sched_job->base.sched->name);
476+
__string(ring, sched_job->base.sched->name)
477477
__field(uint64_t, id)
478478
__field(struct dma_fence *, fence)
479479
__field(uint64_t, ctx)

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 54 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1785,27 +1785,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
17851785
WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
17861786
}
17871787

1788-
static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
1788+
static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
17891789
{
1790+
int r;
1791+
1792+
if (adev->in_gpu_reset) {
1793+
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1794+
if (r)
1795+
return r;
1796+
1797+
r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
1798+
(void **)&adev->gfx.rlc.cs_ptr);
1799+
if (!r) {
1800+
adev->gfx.rlc.funcs->get_csb_buffer(adev,
1801+
adev->gfx.rlc.cs_ptr);
1802+
amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1803+
}
1804+
1805+
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1806+
if (r)
1807+
return r;
1808+
}
1809+
17901810
/* csib */
17911811
WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
17921812
adev->gfx.rlc.clear_state_gpu_addr >> 32);
17931813
WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
17941814
adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
17951815
WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1816+
1817+
return 0;
17961818
}
17971819

1798-
static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
1820+
static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
17991821
{
18001822
int i;
1823+
int r;
18011824

1802-
gfx_v10_0_init_csb(adev);
1825+
r = gfx_v10_0_init_csb(adev);
1826+
if (r)
1827+
return r;
18031828

18041829
for (i = 0; i < adev->num_vmhubs; i++)
18051830
amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
18061831

18071832
/* TODO: init power gating */
1808-
return;
1833+
return 0;
18091834
}
18101835

18111836
void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
@@ -1907,7 +1932,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
19071932
r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
19081933
if (r)
19091934
return r;
1910-
gfx_v10_0_init_pg(adev);
1935+
1936+
r = gfx_v10_0_init_pg(adev);
1937+
if (r)
1938+
return r;
19111939

19121940
/* enable RLC SRM */
19131941
gfx_v10_0_rlc_enable_srm(adev);
@@ -1933,7 +1961,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
19331961
return r;
19341962
}
19351963

1936-
gfx_v10_0_init_pg(adev);
1964+
r = gfx_v10_0_init_pg(adev);
1965+
if (r)
1966+
return r;
1967+
19371968
adev->gfx.rlc.funcs->start(adev);
19381969

19391970
if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
@@ -2400,7 +2431,7 @@ static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
24002431
return 0;
24012432
}
24022433

2403-
static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2434+
static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
24042435
{
24052436
int i;
24062437
u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
@@ -2413,7 +2444,17 @@ static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
24132444
adev->gfx.gfx_ring[i].sched.ready = false;
24142445
}
24152446
WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2416-
udelay(50);
2447+
2448+
for (i = 0; i < adev->usec_timeout; i++) {
2449+
if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
2450+
break;
2451+
udelay(1);
2452+
}
2453+
2454+
if (i >= adev->usec_timeout)
2455+
DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2456+
2457+
return 0;
24172458
}
24182459

24192460
static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
@@ -3114,6 +3155,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
31143155
{
31153156
struct amdgpu_device *adev = ring->adev;
31163157
struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3158+
int mqd_idx = ring - &adev->gfx.gfx_ring[0];
31173159

31183160
if (!adev->in_gpu_reset && !adev->in_suspend) {
31193161
memset((void *)mqd, 0, sizeof(*mqd));
@@ -3125,12 +3167,12 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
31253167
#endif
31263168
nv_grbm_select(adev, 0, 0, 0, 0);
31273169
mutex_unlock(&adev->srbm_mutex);
3128-
if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
3129-
memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd));
3170+
if (adev->gfx.me.mqd_backup[mqd_idx])
3171+
memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
31303172
} else if (adev->in_gpu_reset) {
31313173
/* reset mqd with the backup copy */
3132-
if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
3133-
memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
3174+
if (adev->gfx.me.mqd_backup[mqd_idx])
3175+
memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
31343176
/* reset the ring */
31353177
ring->wptr = 0;
31363178
adev->wb.wb[ring->wptr_offs] = 0;

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