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Kyung Min Parkjoergroedel
Kyung Min Park
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joergroedel
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iommu/vt-d: Audit IOMMU Capabilities and add helper functions
Audit IOMMU Capability/Extended Capability and check if the IOMMUs have the consistent value for features. Report out or scale to the lowest supported when IOMMU features have incompatibility among IOMMUs. Report out features when below features are mismatched: - First Level 5 Level Paging Support (FL5LP) - First Level 1 GByte Page Support (FL1GP) - Read Draining (DRD) - Write Draining (DWD) - Page Selective Invalidation (PSI) - Zero Length Read (ZLR) - Caching Mode (CM) - Protected High/Low-Memory Region (PHMR/PLMR) - Required Write-Buffer Flushing (RWBF) - Advanced Fault Logging (AFL) - RID-PASID Support (RPS) - Scalable Mode Page Walk Coherency (SMPWC) - First Level Translation Support (FLTS) - Second Level Translation Support (SLTS) - No Write Flag Support (NWFS) - Second Level Accessed/Dirty Support (SLADS) - Virtual Command Support (VCS) - Scalable Mode Translation Support (SMTS) - Device TLB Invalidation Throttle (DIT) - Page Drain Support (PDS) - Process Address Space ID Support (PASID) - Extended Accessed Flag Support (EAFS) - Supervisor Request Support (SRS) - Execute Request Support (ERS) - Page Request Support (PRS) - Nested Translation Support (NEST) - Snoop Control (SC) - Pass Through (PT) - Device TLB Support (DT) - Queued Invalidation (QI) - Page walk Coherency (C) Set capability to the lowest supported when below features are mismatched: - Maximum Address Mask Value (MAMV) - Number of Fault Recording Registers (NFR) - Second Level Large Page Support (SLLPS) - Fault Recording Offset (FRO) - Maximum Guest Address Width (MGAW) - Supported Adjusted Guest Address Width (SAGAW) - Number of Domains supported (NDOMS) - Pasid Size Supported (PSS) - Maximum Handle Mask Value (MHMV) - IOTLB Register Offset (IRO) Signed-off-by: Kyung Min Park <[email protected]> Signed-off-by: Lu Baolu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
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‎drivers/iommu/intel/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# SPDX-License-Identifier: GPL-2.0
22
obj-$(CONFIG_DMAR_TABLE) += dmar.o
33
obj-$(CONFIG_INTEL_IOMMU) += iommu.o pasid.o
4-
obj-$(CONFIG_DMAR_TABLE) += trace.o
4+
obj-$(CONFIG_DMAR_TABLE) += trace.o cap_audit.o
55
obj-$(CONFIG_INTEL_IOMMU_DEBUGFS) += debugfs.o
66
obj-$(CONFIG_INTEL_IOMMU_SVM) += svm.o
77
obj-$(CONFIG_IRQ_REMAP) += irq_remapping.o

‎drivers/iommu/intel/cap_audit.c

Lines changed: 185 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,185 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* cap_audit.c - audit iommu capabilities for boot time and hot plug
4+
*
5+
* Copyright (C) 2021 Intel Corporation
6+
*
7+
* Author: Kyung Min Park <[email protected]>
8+
* Lu Baolu <[email protected]>
9+
*/
10+
11+
#define pr_fmt(fmt) "DMAR: " fmt
12+
13+
#include <linux/intel-iommu.h>
14+
#include "cap_audit.h"
15+
16+
static u64 intel_iommu_cap_sanity;
17+
static u64 intel_iommu_ecap_sanity;
18+
19+
static inline void check_irq_capabilities(struct intel_iommu *a,
20+
struct intel_iommu *b)
21+
{
22+
CHECK_FEATURE_MISMATCH(a, b, cap, pi_support, CAP_PI_MASK);
23+
CHECK_FEATURE_MISMATCH(a, b, ecap, eim_support, ECAP_EIM_MASK);
24+
}
25+
26+
static inline void check_dmar_capabilities(struct intel_iommu *a,
27+
struct intel_iommu *b)
28+
{
29+
MINIMAL_FEATURE_IOMMU(b, cap, CAP_MAMV_MASK);
30+
MINIMAL_FEATURE_IOMMU(b, cap, CAP_NFR_MASK);
31+
MINIMAL_FEATURE_IOMMU(b, cap, CAP_SLLPS_MASK);
32+
MINIMAL_FEATURE_IOMMU(b, cap, CAP_FRO_MASK);
33+
MINIMAL_FEATURE_IOMMU(b, cap, CAP_MGAW_MASK);
34+
MINIMAL_FEATURE_IOMMU(b, cap, CAP_SAGAW_MASK);
35+
MINIMAL_FEATURE_IOMMU(b, cap, CAP_NDOMS_MASK);
36+
MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_PSS_MASK);
37+
MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_MHMV_MASK);
38+
MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_IRO_MASK);
39+
40+
CHECK_FEATURE_MISMATCH(a, b, cap, 5lp_support, CAP_FL5LP_MASK);
41+
CHECK_FEATURE_MISMATCH(a, b, cap, fl1gp_support, CAP_FL1GP_MASK);
42+
CHECK_FEATURE_MISMATCH(a, b, cap, read_drain, CAP_RD_MASK);
43+
CHECK_FEATURE_MISMATCH(a, b, cap, write_drain, CAP_WD_MASK);
44+
CHECK_FEATURE_MISMATCH(a, b, cap, pgsel_inv, CAP_PSI_MASK);
45+
CHECK_FEATURE_MISMATCH(a, b, cap, zlr, CAP_ZLR_MASK);
46+
CHECK_FEATURE_MISMATCH(a, b, cap, caching_mode, CAP_CM_MASK);
47+
CHECK_FEATURE_MISMATCH(a, b, cap, phmr, CAP_PHMR_MASK);
48+
CHECK_FEATURE_MISMATCH(a, b, cap, plmr, CAP_PLMR_MASK);
49+
CHECK_FEATURE_MISMATCH(a, b, cap, rwbf, CAP_RWBF_MASK);
50+
CHECK_FEATURE_MISMATCH(a, b, cap, afl, CAP_AFL_MASK);
51+
CHECK_FEATURE_MISMATCH(a, b, ecap, rps, ECAP_RPS_MASK);
52+
CHECK_FEATURE_MISMATCH(a, b, ecap, smpwc, ECAP_SMPWC_MASK);
53+
CHECK_FEATURE_MISMATCH(a, b, ecap, flts, ECAP_FLTS_MASK);
54+
CHECK_FEATURE_MISMATCH(a, b, ecap, slts, ECAP_SLTS_MASK);
55+
CHECK_FEATURE_MISMATCH(a, b, ecap, nwfs, ECAP_NWFS_MASK);
56+
CHECK_FEATURE_MISMATCH(a, b, ecap, slads, ECAP_SLADS_MASK);
57+
CHECK_FEATURE_MISMATCH(a, b, ecap, vcs, ECAP_VCS_MASK);
58+
CHECK_FEATURE_MISMATCH(a, b, ecap, smts, ECAP_SMTS_MASK);
59+
CHECK_FEATURE_MISMATCH(a, b, ecap, pds, ECAP_PDS_MASK);
60+
CHECK_FEATURE_MISMATCH(a, b, ecap, dit, ECAP_DIT_MASK);
61+
CHECK_FEATURE_MISMATCH(a, b, ecap, pasid, ECAP_PASID_MASK);
62+
CHECK_FEATURE_MISMATCH(a, b, ecap, eafs, ECAP_EAFS_MASK);
63+
CHECK_FEATURE_MISMATCH(a, b, ecap, srs, ECAP_SRS_MASK);
64+
CHECK_FEATURE_MISMATCH(a, b, ecap, ers, ECAP_ERS_MASK);
65+
CHECK_FEATURE_MISMATCH(a, b, ecap, prs, ECAP_PRS_MASK);
66+
CHECK_FEATURE_MISMATCH(a, b, ecap, nest, ECAP_NEST_MASK);
67+
CHECK_FEATURE_MISMATCH(a, b, ecap, mts, ECAP_MTS_MASK);
68+
CHECK_FEATURE_MISMATCH(a, b, ecap, sc_support, ECAP_SC_MASK);
69+
CHECK_FEATURE_MISMATCH(a, b, ecap, pass_through, ECAP_PT_MASK);
70+
CHECK_FEATURE_MISMATCH(a, b, ecap, dev_iotlb_support, ECAP_DT_MASK);
71+
CHECK_FEATURE_MISMATCH(a, b, ecap, qis, ECAP_QI_MASK);
72+
CHECK_FEATURE_MISMATCH(a, b, ecap, coherent, ECAP_C_MASK);
73+
}
74+
75+
static int cap_audit_hotplug(struct intel_iommu *iommu, enum cap_audit_type type)
76+
{
77+
bool mismatch = false;
78+
u64 old_cap = intel_iommu_cap_sanity;
79+
u64 old_ecap = intel_iommu_ecap_sanity;
80+
81+
if (type == CAP_AUDIT_HOTPLUG_IRQR) {
82+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, pi_support, CAP_PI_MASK);
83+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, eim_support, ECAP_EIM_MASK);
84+
goto out;
85+
}
86+
87+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, 5lp_support, CAP_FL5LP_MASK);
88+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl1gp_support, CAP_FL1GP_MASK);
89+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, read_drain, CAP_RD_MASK);
90+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, write_drain, CAP_WD_MASK);
91+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, pgsel_inv, CAP_PSI_MASK);
92+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, zlr, CAP_ZLR_MASK);
93+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, caching_mode, CAP_CM_MASK);
94+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, phmr, CAP_PHMR_MASK);
95+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, plmr, CAP_PLMR_MASK);
96+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, rwbf, CAP_RWBF_MASK);
97+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, afl, CAP_AFL_MASK);
98+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, rps, ECAP_RPS_MASK);
99+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, smpwc, ECAP_SMPWC_MASK);
100+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, flts, ECAP_FLTS_MASK);
101+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, slts, ECAP_SLTS_MASK);
102+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, nwfs, ECAP_NWFS_MASK);
103+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, slads, ECAP_SLADS_MASK);
104+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, vcs, ECAP_VCS_MASK);
105+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, smts, ECAP_SMTS_MASK);
106+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pds, ECAP_PDS_MASK);
107+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, dit, ECAP_DIT_MASK);
108+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pasid, ECAP_PASID_MASK);
109+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, eafs, ECAP_EAFS_MASK);
110+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, srs, ECAP_SRS_MASK);
111+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, ers, ECAP_ERS_MASK);
112+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, prs, ECAP_PRS_MASK);
113+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, nest, ECAP_NEST_MASK);
114+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, mts, ECAP_MTS_MASK);
115+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, sc_support, ECAP_SC_MASK);
116+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pass_through, ECAP_PT_MASK);
117+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, dev_iotlb_support, ECAP_DT_MASK);
118+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, qis, ECAP_QI_MASK);
119+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, coherent, ECAP_C_MASK);
120+
121+
/* Abort hot plug if the hot plug iommu feature is smaller than global */
122+
MINIMAL_FEATURE_HOTPLUG(iommu, cap, max_amask_val, CAP_MAMV_MASK, mismatch);
123+
MINIMAL_FEATURE_HOTPLUG(iommu, cap, num_fault_regs, CAP_NFR_MASK, mismatch);
124+
MINIMAL_FEATURE_HOTPLUG(iommu, cap, super_page_val, CAP_SLLPS_MASK, mismatch);
125+
MINIMAL_FEATURE_HOTPLUG(iommu, cap, fault_reg_offset, CAP_FRO_MASK, mismatch);
126+
MINIMAL_FEATURE_HOTPLUG(iommu, cap, mgaw, CAP_MGAW_MASK, mismatch);
127+
MINIMAL_FEATURE_HOTPLUG(iommu, cap, sagaw, CAP_SAGAW_MASK, mismatch);
128+
MINIMAL_FEATURE_HOTPLUG(iommu, cap, ndoms, CAP_NDOMS_MASK, mismatch);
129+
MINIMAL_FEATURE_HOTPLUG(iommu, ecap, pss, ECAP_PSS_MASK, mismatch);
130+
MINIMAL_FEATURE_HOTPLUG(iommu, ecap, max_handle_mask, ECAP_MHMV_MASK, mismatch);
131+
MINIMAL_FEATURE_HOTPLUG(iommu, ecap, iotlb_offset, ECAP_IRO_MASK, mismatch);
132+
133+
out:
134+
if (mismatch) {
135+
intel_iommu_cap_sanity = old_cap;
136+
intel_iommu_ecap_sanity = old_ecap;
137+
return -EFAULT;
138+
}
139+
140+
return 0;
141+
}
142+
143+
static int cap_audit_static(struct intel_iommu *iommu, enum cap_audit_type type)
144+
{
145+
struct dmar_drhd_unit *d;
146+
struct intel_iommu *i;
147+
148+
rcu_read_lock();
149+
if (list_empty(&dmar_drhd_units))
150+
goto out;
151+
152+
for_each_active_iommu(i, d) {
153+
if (!iommu) {
154+
intel_iommu_ecap_sanity = i->ecap;
155+
intel_iommu_cap_sanity = i->cap;
156+
iommu = i;
157+
continue;
158+
}
159+
160+
if (type == CAP_AUDIT_STATIC_DMAR)
161+
check_dmar_capabilities(iommu, i);
162+
else
163+
check_irq_capabilities(iommu, i);
164+
}
165+
166+
out:
167+
rcu_read_unlock();
168+
return 0;
169+
}
170+
171+
int intel_cap_audit(enum cap_audit_type type, struct intel_iommu *iommu)
172+
{
173+
switch (type) {
174+
case CAP_AUDIT_STATIC_DMAR:
175+
case CAP_AUDIT_STATIC_IRQR:
176+
return cap_audit_static(iommu, type);
177+
case CAP_AUDIT_HOTPLUG_DMAR:
178+
case CAP_AUDIT_HOTPLUG_IRQR:
179+
return cap_audit_hotplug(iommu, type);
180+
default:
181+
break;
182+
}
183+
184+
return -EFAULT;
185+
}

‎drivers/iommu/intel/cap_audit.h

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,110 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* cap_audit.h - audit iommu capabilities header
4+
*
5+
* Copyright (C) 2021 Intel Corporation
6+
*
7+
* Author: Kyung Min Park <[email protected]>
8+
*/
9+
10+
/*
11+
* Capability Register Mask
12+
*/
13+
#define CAP_FL5LP_MASK BIT_ULL(60)
14+
#define CAP_PI_MASK BIT_ULL(59)
15+
#define CAP_FL1GP_MASK BIT_ULL(56)
16+
#define CAP_RD_MASK BIT_ULL(55)
17+
#define CAP_WD_MASK BIT_ULL(54)
18+
#define CAP_MAMV_MASK GENMASK_ULL(53, 48)
19+
#define CAP_NFR_MASK GENMASK_ULL(47, 40)
20+
#define CAP_PSI_MASK BIT_ULL(39)
21+
#define CAP_SLLPS_MASK GENMASK_ULL(37, 34)
22+
#define CAP_FRO_MASK GENMASK_ULL(33, 24)
23+
#define CAP_ZLR_MASK BIT_ULL(22)
24+
#define CAP_MGAW_MASK GENMASK_ULL(21, 16)
25+
#define CAP_SAGAW_MASK GENMASK_ULL(12, 8)
26+
#define CAP_CM_MASK BIT_ULL(7)
27+
#define CAP_PHMR_MASK BIT_ULL(6)
28+
#define CAP_PLMR_MASK BIT_ULL(5)
29+
#define CAP_RWBF_MASK BIT_ULL(4)
30+
#define CAP_AFL_MASK BIT_ULL(3)
31+
#define CAP_NDOMS_MASK GENMASK_ULL(2, 0)
32+
33+
/*
34+
* Extended Capability Register Mask
35+
*/
36+
#define ECAP_RPS_MASK BIT_ULL(49)
37+
#define ECAP_SMPWC_MASK BIT_ULL(48)
38+
#define ECAP_FLTS_MASK BIT_ULL(47)
39+
#define ECAP_SLTS_MASK BIT_ULL(46)
40+
#define ECAP_SLADS_MASK BIT_ULL(45)
41+
#define ECAP_VCS_MASK BIT_ULL(44)
42+
#define ECAP_SMTS_MASK BIT_ULL(43)
43+
#define ECAP_PDS_MASK BIT_ULL(42)
44+
#define ECAP_DIT_MASK BIT_ULL(41)
45+
#define ECAP_PASID_MASK BIT_ULL(40)
46+
#define ECAP_PSS_MASK GENMASK_ULL(39, 35)
47+
#define ECAP_EAFS_MASK BIT_ULL(34)
48+
#define ECAP_NWFS_MASK BIT_ULL(33)
49+
#define ECAP_SRS_MASK BIT_ULL(31)
50+
#define ECAP_ERS_MASK BIT_ULL(30)
51+
#define ECAP_PRS_MASK BIT_ULL(29)
52+
#define ECAP_NEST_MASK BIT_ULL(26)
53+
#define ECAP_MTS_MASK BIT_ULL(25)
54+
#define ECAP_MHMV_MASK GENMASK_ULL(23, 20)
55+
#define ECAP_IRO_MASK GENMASK_ULL(17, 8)
56+
#define ECAP_SC_MASK BIT_ULL(7)
57+
#define ECAP_PT_MASK BIT_ULL(6)
58+
#define ECAP_EIM_MASK BIT_ULL(4)
59+
#define ECAP_DT_MASK BIT_ULL(2)
60+
#define ECAP_QI_MASK BIT_ULL(1)
61+
#define ECAP_C_MASK BIT_ULL(0)
62+
63+
/*
64+
* u64 intel_iommu_cap_sanity, intel_iommu_ecap_sanity will be adjusted as each
65+
* IOMMU gets audited.
66+
*/
67+
#define DO_CHECK_FEATURE_MISMATCH(a, b, cap, feature, MASK) \
68+
do { \
69+
if (cap##_##feature(a) != cap##_##feature(b)) { \
70+
intel_iommu_##cap##_sanity &= ~(MASK); \
71+
pr_info("IOMMU feature %s inconsistent", #feature); \
72+
} \
73+
} while (0)
74+
75+
#define CHECK_FEATURE_MISMATCH(a, b, cap, feature, MASK) \
76+
DO_CHECK_FEATURE_MISMATCH((a)->cap, (b)->cap, cap, feature, MASK)
77+
78+
#define CHECK_FEATURE_MISMATCH_HOTPLUG(b, cap, feature, MASK) \
79+
do { \
80+
if (cap##_##feature(intel_iommu_##cap##_sanity)) \
81+
DO_CHECK_FEATURE_MISMATCH(intel_iommu_##cap##_sanity, \
82+
(b)->cap, cap, feature, MASK); \
83+
} while (0)
84+
85+
#define MINIMAL_FEATURE_IOMMU(iommu, cap, MASK) \
86+
do { \
87+
u64 min_feature = intel_iommu_##cap##_sanity & (MASK); \
88+
min_feature = min_t(u64, min_feature, (iommu)->cap & (MASK)); \
89+
intel_iommu_##cap##_sanity = (intel_iommu_##cap##_sanity & ~(MASK)) | \
90+
min_feature; \
91+
} while (0)
92+
93+
#define MINIMAL_FEATURE_HOTPLUG(iommu, cap, feature, MASK, mismatch) \
94+
do { \
95+
if ((intel_iommu_##cap##_sanity & (MASK)) > \
96+
(cap##_##feature((iommu)->cap))) \
97+
mismatch = true; \
98+
else \
99+
(iommu)->cap = ((iommu)->cap & ~(MASK)) | \
100+
(intel_iommu_##cap##_sanity & (MASK)); \
101+
} while (0)
102+
103+
enum cap_audit_type {
104+
CAP_AUDIT_STATIC_DMAR,
105+
CAP_AUDIT_STATIC_IRQR,
106+
CAP_AUDIT_HOTPLUG_DMAR,
107+
CAP_AUDIT_HOTPLUG_IRQR,
108+
};
109+
110+
int intel_cap_audit(enum cap_audit_type type, struct intel_iommu *iommu);

‎drivers/iommu/intel/iommu.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@
4747

4848
#include "../irq_remapping.h"
4949
#include "pasid.h"
50+
#include "cap_audit.h"
5051

5152
#define ROOT_SIZE VTD_PAGE_SIZE
5253
#define CONTEXT_SIZE VTD_PAGE_SIZE
@@ -3206,6 +3207,10 @@ static int __init init_dmars(void)
32063207
goto error;
32073208
}
32083209

3210+
ret = intel_cap_audit(CAP_AUDIT_STATIC_DMAR, NULL);
3211+
if (ret)
3212+
goto free_iommu;
3213+
32093214
for_each_iommu(iommu, drhd) {
32103215
if (drhd->ignored) {
32113216
iommu_disable_translation(iommu);
@@ -3757,6 +3762,10 @@ static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
37573762
if (g_iommus[iommu->seq_id])
37583763
return 0;
37593764

3765+
ret = intel_cap_audit(CAP_AUDIT_HOTPLUG_DMAR, iommu);
3766+
if (ret)
3767+
goto out;
3768+
37603769
if (hw_pass_through && !ecap_pass_through(iommu->ecap)) {
37613770
pr_warn("%s: Doesn't support hardware pass through.\n",
37623771
iommu->name);

‎drivers/iommu/intel/irq_remapping.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#include <asm/pci-direct.h>
2323

2424
#include "../irq_remapping.h"
25+
#include "cap_audit.h"
2526

2627
enum irq_mode {
2728
IRQ_REMAPPING,
@@ -734,6 +735,9 @@ static int __init intel_prepare_irq_remapping(void)
734735
if (dmar_table_init() < 0)
735736
return -ENODEV;
736737

738+
if (intel_cap_audit(CAP_AUDIT_STATIC_IRQR, NULL))
739+
goto error;
740+
737741
if (!dmar_ir_support())
738742
return -ENODEV;
739743

@@ -1439,6 +1443,10 @@ static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
14391443
int ret;
14401444
int eim = x2apic_enabled();
14411445

1446+
ret = intel_cap_audit(CAP_AUDIT_HOTPLUG_IRQR, iommu);
1447+
if (ret)
1448+
return ret;
1449+
14421450
if (eim && !ecap_eim_support(iommu->ecap)) {
14431451
pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
14441452
iommu->reg_phys, iommu->ecap);

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