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1 parent 2f77da0 commit adf6b91Copy full SHA for adf6b91
drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -73,6 +73,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
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/* Core Clock Outputs */
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DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
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+ DEF_GEN3_Z("zg", R8A774B1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
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DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -120,6 +121,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
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};
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static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
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+ DEF_MOD("3dge", 112, R8A774B1_CLK_ZG),
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DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
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DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
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DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
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