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mellanoxbmcandy-shev
mellanoxbmc
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andy-shev
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platform/x86: mlx-platform: Add more definitions for system attributes
Add new attributes for the all type systems specifying for each equipped CPLD device, the CPLD part number and the CPLD minor version of the device: 'cpld{n}_pn' and 'cpld{n}_version_min'. This information is to be used for mathcing the current CPLD image and for making decision if image upgrade is required for CPLD device. Signed-off-by: Vadim Pasternak <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]>
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‎drivers/platform/x86/mlx-platform.c

Lines changed: 128 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,10 @@
2626
#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
2727
#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
2828
#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
29+
#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04
30+
#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06
31+
#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08
32+
#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a
2933
#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
3034
#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
3135
#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
@@ -72,6 +76,10 @@
7276
#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1
7377
#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2
7478
#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3
79+
#define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde
80+
#define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf
81+
#define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0
82+
#define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1
7583
#define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2
7684
#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
7785
#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
@@ -1303,6 +1311,32 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
13031311
.bit = GENMASK(7, 0),
13041312
.mode = 0444,
13051313
},
1314+
{
1315+
.label = "cpld1_pn",
1316+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
1317+
.bit = GENMASK(15, 0),
1318+
.mode = 0444,
1319+
.regnum = 2,
1320+
},
1321+
{
1322+
.label = "cpld2_pn",
1323+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
1324+
.bit = GENMASK(15, 0),
1325+
.mode = 0444,
1326+
.regnum = 2,
1327+
},
1328+
{
1329+
.label = "cpld1_version_min",
1330+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
1331+
.bit = GENMASK(7, 0),
1332+
.mode = 0444,
1333+
},
1334+
{
1335+
.label = "cpld2_version_min",
1336+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
1337+
.bit = GENMASK(7, 0),
1338+
.mode = 0444,
1339+
},
13061340
{
13071341
.label = "reset_long_pb",
13081342
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
@@ -1409,6 +1443,32 @@ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
14091443
.bit = GENMASK(7, 0),
14101444
.mode = 0444,
14111445
},
1446+
{
1447+
.label = "cpld1_pn",
1448+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
1449+
.bit = GENMASK(15, 0),
1450+
.mode = 0444,
1451+
.regnum = 2,
1452+
},
1453+
{
1454+
.label = "cpld2_pn",
1455+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
1456+
.bit = GENMASK(15, 0),
1457+
.mode = 0444,
1458+
.regnum = 2,
1459+
},
1460+
{
1461+
.label = "cpld1_version_min",
1462+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
1463+
.bit = GENMASK(7, 0),
1464+
.mode = 0444,
1465+
},
1466+
{
1467+
.label = "cpld2_version_min",
1468+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
1469+
.bit = GENMASK(7, 0),
1470+
.mode = 0444,
1471+
},
14121472
{
14131473
.label = "reset_long_pb",
14141474
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
@@ -1527,6 +1587,58 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
15271587
.bit = GENMASK(7, 0),
15281588
.mode = 0444,
15291589
},
1590+
{
1591+
.label = "cpld1_pn",
1592+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
1593+
.bit = GENMASK(15, 0),
1594+
.mode = 0444,
1595+
.regnum = 2,
1596+
},
1597+
{
1598+
.label = "cpld2_pn",
1599+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
1600+
.bit = GENMASK(15, 0),
1601+
.mode = 0444,
1602+
.regnum = 2,
1603+
},
1604+
{
1605+
.label = "cpld3_pn",
1606+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
1607+
.bit = GENMASK(15, 0),
1608+
.mode = 0444,
1609+
.regnum = 2,
1610+
},
1611+
{
1612+
.label = "cpld4_pn",
1613+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
1614+
.bit = GENMASK(15, 0),
1615+
.mode = 0444,
1616+
.regnum = 2,
1617+
},
1618+
{
1619+
.label = "cpld1_version_min",
1620+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
1621+
.bit = GENMASK(7, 0),
1622+
.mode = 0444,
1623+
},
1624+
{
1625+
.label = "cpld2_version_min",
1626+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
1627+
.bit = GENMASK(7, 0),
1628+
.mode = 0444,
1629+
},
1630+
{
1631+
.label = "cpld3_version_min",
1632+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
1633+
.bit = GENMASK(7, 0),
1634+
.mode = 0444,
1635+
},
1636+
{
1637+
.label = "cpld4_version_min",
1638+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
1639+
.bit = GENMASK(7, 0),
1640+
.mode = 0444,
1641+
},
15301642
{
15311643
.label = "reset_long_pb",
15321644
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
@@ -2006,6 +2118,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
20062118
case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
20072119
case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
20082120
case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
2121+
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
2122+
case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
2123+
case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
2124+
case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
20092125
case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
20102126
case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
20112127
case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
@@ -2051,6 +2167,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
20512167
case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
20522168
case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
20532169
case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
2170+
case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
2171+
case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
2172+
case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
2173+
case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
20542174
case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
20552175
case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
20562176
case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
@@ -2085,6 +2205,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
20852205
case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
20862206
case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
20872207
case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
2208+
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
2209+
case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
2210+
case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
2211+
case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
20882212
case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
20892213
case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
20902214
case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
@@ -2122,6 +2246,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
21222246
case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
21232247
case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
21242248
case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
2249+
case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
2250+
case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
2251+
case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
2252+
case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
21252253
case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
21262254
case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
21272255
case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:

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