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Commit af688a9

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Bharat BhushanPaolo Abeni
authored andcommitted
octeontx2-af: Fix CPT AF register offset calculation
Some CPT AF registers are per LF and others are global. Translation of PF/VF local LF slot number to actual LF slot number is required only for accessing perf LF registers. CPT AF global registers access do not require any LF slot number. Also, there is no reason CPT PF/VF to know actual lf's register offset. Without this fix microcode loading will fail, VFs cannot be created and hardware is not usable. Fixes: bc35e28 ("octeontx2-af: replace cpt slot with lf id on reg write") Signed-off-by: Bharat Bhushan <[email protected]> Reviewed-by: Simon Horman <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
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  • drivers/net/ethernet/marvell/octeontx2/af

1 file changed

+11
-12
lines changed

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -632,7 +632,9 @@ int rvu_mbox_handler_cpt_inline_ipsec_cfg(struct rvu *rvu,
632632
return ret;
633633
}
634634

635-
static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)
635+
static bool validate_and_update_reg_offset(struct rvu *rvu,
636+
struct cpt_rd_wr_reg_msg *req,
637+
u64 *reg_offset)
636638
{
637639
u64 offset = req->reg_offset;
638640
int blkaddr, num_lfs, lf;
@@ -663,6 +665,11 @@ static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)
663665
if (lf < 0)
664666
return false;
665667

668+
/* Translate local LF's offset to global CPT LF's offset to
669+
* access LFX register.
670+
*/
671+
*reg_offset = (req->reg_offset & 0xFF000) + (lf << 3);
672+
666673
return true;
667674
} else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) {
668675
/* Registers that can be accessed from PF */
@@ -697,7 +704,7 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu,
697704
struct cpt_rd_wr_reg_msg *rsp)
698705
{
699706
u64 offset = req->reg_offset;
700-
int blkaddr, lf;
707+
int blkaddr;
701708

702709
blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
703710
if (blkaddr < 0)
@@ -708,18 +715,10 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu,
708715
!is_cpt_vf(rvu, req->hdr.pcifunc))
709716
return CPT_AF_ERR_ACCESS_DENIED;
710717

711-
if (!is_valid_offset(rvu, req))
718+
if (!validate_and_update_reg_offset(rvu, req, &offset))
712719
return CPT_AF_ERR_ACCESS_DENIED;
713720

714-
/* Translate local LF used by VFs to global CPT LF */
715-
lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr], req->hdr.pcifunc,
716-
(offset & 0xFFF) >> 3);
717-
718-
/* Translate local LF's offset to global CPT LF's offset */
719-
offset &= 0xFF000;
720-
offset += lf << 3;
721-
722-
rsp->reg_offset = offset;
721+
rsp->reg_offset = req->reg_offset;
723722
rsp->ret_val = req->ret_val;
724723
rsp->is_write = req->is_write;
725724

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