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Nitin Rawatvinodkoul
Nitin Rawat
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vinodkoul
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phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750
Add SM8750 specific register layout and table configs. The serdes TX RX register offset has changed for SM8750 and hence keep UFS specific serdes offsets in a dedicated header file. Reviewed-by: Neil Armstrong <[email protected]> Co-developed-by: Manish Pandey <[email protected]> Signed-off-by: Manish Pandey <[email protected]> Signed-off-by: Nitin Rawat <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,4 +86,11 @@
8686
#define QSERDES_V6_COM_CMN_STATUS 0x1d0
8787
#define QSERDES_V6_COM_C_READY_STATUS 0x1f8
8888

89+
#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268
90+
#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
91+
#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
92+
#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
93+
#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
94+
#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
95+
#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
8996
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* Copyright (c) 2024, Linaro Limited
4+
*/
5+
6+
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
7+
#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
8+
9+
#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
10+
#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
11+
#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
12+
#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
13+
#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
14+
#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
15+
16+
#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
17+
#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
18+
#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
19+
#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
20+
#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
21+
#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xc4
22+
#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xd4
23+
#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xdc
24+
#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xf0
25+
#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xf4
26+
#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
27+
#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1b4
28+
#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1cc
29+
#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1d4
30+
#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1f0
31+
#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
32+
#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
33+
#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
34+
#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
35+
#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
36+
#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
37+
#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
38+
#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
39+
#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
40+
#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
41+
#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
42+
#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
43+
#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
44+
#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26c
45+
#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
46+
#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
47+
#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27c
48+
#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
49+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
50+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
51+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28c
52+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
53+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
54+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
55+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29c
56+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2a0
57+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2a8
58+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2ac
59+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2b0
60+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2b4
61+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2b8
62+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2bc
63+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2c0
64+
#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2c4
65+
#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
66+
#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
67+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

Lines changed: 172 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131
#include "phy-qcom-qmp-pcs-ufs-v6.h"
3232

3333
#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
34+
#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
3435

3536
/* QPHY_PCS_READY_STATUS bit */
3637
#define PCS_READY BIT(0)
@@ -949,6 +950,124 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
949950
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
950951
};
951952

953+
static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
954+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
955+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
956+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
957+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
958+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
959+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
960+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
961+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f),
962+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
963+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
964+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
965+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
966+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
967+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
968+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
969+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
970+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
971+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
972+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
973+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
974+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
975+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
976+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
977+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
978+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
979+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
980+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
981+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
982+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
983+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
984+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
985+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
986+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
987+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe),
988+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
989+
};
990+
991+
static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
992+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
993+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
994+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
995+
};
996+
997+
static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
998+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0c),
999+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0c),
1000+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
1001+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
1002+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
1003+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
1004+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
1005+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
1006+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
1007+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8e),
1008+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1009+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xce),
1010+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xce),
1011+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
1012+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1a),
1013+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0f),
1014+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
1015+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
1016+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9a),
1017+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xe2),
1018+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
1019+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1b),
1020+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1b),
1021+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
1022+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9b),
1023+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2a),
1024+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
1025+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
1026+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
1027+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
1028+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
1029+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
1030+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
1031+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5f),
1032+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
1033+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xe3),
1034+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
1035+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9b),
1036+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9b),
1037+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
1038+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
1039+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5f),
1040+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
1041+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xfb),
1042+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
1043+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1f),
1044+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
1045+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xfa),
1046+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
1047+
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
1048+
};
1049+
1050+
static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
1051+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1052+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1053+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
1054+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
1055+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
1056+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e),
1057+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
1058+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
1059+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
1060+
};
1061+
1062+
static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
1063+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
1064+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
1065+
};
1066+
1067+
static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
1068+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
1069+
};
1070+
9521071
struct qmp_ufs_offsets {
9531072
u16 serdes;
9541073
u16 pcs;
@@ -1523,6 +1642,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
15231642
.regs = ufsphy_v6_regs_layout,
15241643
};
15251644

1645+
static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
1646+
.lanes = 2,
1647+
1648+
.offsets = &qmp_ufs_offsets_v6,
1649+
.max_supported_gear = UFS_HS_G5,
1650+
1651+
.tbls = {
1652+
.serdes = sm8750_ufsphy_serdes,
1653+
.serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
1654+
.tx = sm8750_ufsphy_tx,
1655+
.tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
1656+
.rx = sm8750_ufsphy_rx,
1657+
.rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
1658+
.pcs = sm8750_ufsphy_pcs,
1659+
.pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
1660+
},
1661+
1662+
.tbls_hs_b = {
1663+
.pcs = sm8750_ufsphy_hs_b_pcs,
1664+
.pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
1665+
},
1666+
1667+
.tbls_hs_overlay[0] = {
1668+
.pcs = sm8750_ufsphy_g4_pcs,
1669+
.pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
1670+
.max_gear = UFS_HS_G4,
1671+
},
1672+
.tbls_hs_overlay[1] = {
1673+
.pcs = sm8650_ufsphy_g5_pcs,
1674+
.pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs),
1675+
.max_gear = UFS_HS_G5,
1676+
},
1677+
1678+
.vreg_list = qmp_phy_vreg_l,
1679+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1680+
.regs = ufsphy_v6_regs_layout,
1681+
1682+
};
1683+
15261684
static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
15271685
{
15281686
void __iomem *serdes = qmp->serdes;
@@ -1578,23 +1736,25 @@ static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cf
15781736
return ret;
15791737
}
15801738

1739+
static void qmp_ufs_init_all(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1740+
{
1741+
qmp_ufs_serdes_init(qmp, tbls);
1742+
qmp_ufs_lanes_init(qmp, tbls);
1743+
qmp_ufs_pcs_init(qmp, tbls);
1744+
}
1745+
15811746
static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
15821747
{
15831748
int i;
15841749

1585-
qmp_ufs_serdes_init(qmp, &cfg->tbls);
1586-
qmp_ufs_lanes_init(qmp, &cfg->tbls);
1587-
qmp_ufs_pcs_init(qmp, &cfg->tbls);
1750+
qmp_ufs_init_all(qmp, &cfg->tbls);
15881751

15891752
i = qmp_ufs_get_gear_overlay(qmp, cfg);
15901753
if (i >= 0) {
1591-
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
1592-
qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
1593-
qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
1754+
qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]);
15941755
}
15951756

1596-
if (qmp->mode == PHY_MODE_UFS_HS_B)
1597-
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
1757+
qmp_ufs_init_all(qmp, &cfg->tbls_hs_b);
15981758
}
15991759

16001760
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -2061,7 +2221,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
20612221
}, {
20622222
.compatible = "qcom,sm8650-qmp-ufs-phy",
20632223
.data = &sm8650_ufsphy_cfg,
2224+
}, {
2225+
.compatible = "qcom,sm8750-qmp-ufs-phy",
2226+
.data = &sm8750_ufsphy_cfg,
20642227
},
2228+
20652229
{ },
20662230
};
20672231
MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);

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