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53 | 53 | #include "intel_vdsc.h"
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54 | 54 | #include "skl_scaler.h"
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55 | 55 |
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| 56 | +/* |
| 57 | + * DP MST (DisplayPort Multi-Stream Transport) |
| 58 | + * |
| 59 | + * MST support on the source depends on the platform and port. DP initialization |
| 60 | + * sets up MST for each MST capable encoder. This will become the primary |
| 61 | + * encoder for the port. |
| 62 | + * |
| 63 | + * MST initialization of each primary encoder creates MST stream encoders, one |
| 64 | + * per pipe, and initializes the MST topology manager. The MST stream encoders |
| 65 | + * are sometimes called "fake encoders", because they're virtual, not |
| 66 | + * physical. Thus there are (number of MST capable ports) x (number of pipes) |
| 67 | + * MST stream encoders in total. |
| 68 | + * |
| 69 | + * Decision to use MST for a sink happens at detect on the connector attached to |
| 70 | + * the primary encoder, and this will not change while the sink is connected. We |
| 71 | + * always use MST when possible, including for SST sinks with sideband messaging |
| 72 | + * support. |
| 73 | + * |
| 74 | + * The connectors for the MST streams are added and removed dynamically by the |
| 75 | + * topology manager. Their connection status is also determined by the topology |
| 76 | + * manager. |
| 77 | + * |
| 78 | + * On hardware, each transcoder may be associated with a single DDI |
| 79 | + * port. Multiple transcoders may be associated with the same DDI port only if |
| 80 | + * the port is in MST mode. |
| 81 | + * |
| 82 | + * On TGL+, all the transcoders streaming on the same DDI port will indicate a |
| 83 | + * primary transcoder; the TGL_DP_TP_CTL and TGL_DP_TP_STATUS registers are |
| 84 | + * relevant only on the primary transcoder. Prior to that, they are port |
| 85 | + * registers. |
| 86 | + */ |
| 87 | + |
56 | 88 | /* From fake MST stream encoder to primary encoder */
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57 | 89 | static struct intel_encoder *to_primary_encoder(struct intel_encoder *encoder)
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58 | 90 | {
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