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Weili Qianherbertx
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crypto: hisilicon/qm - inject error before stopping queue
The master ooo cannot be completely closed when the accelerator core reports memory error. Therefore, the driver needs to inject the qm error to close the master ooo. Currently, the qm error is injected after stopping queue, memory may be released immediately after stopping queue, causing the device to access the released memory. Therefore, error is injected to close master ooo before stopping queue to ensure that the device does not access the released memory. Fixes: 6c6dd58 ("crypto: hisilicon/qm - add controller reset interface") Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
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  • drivers/crypto/hisilicon

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drivers/crypto/hisilicon/qm.c

Lines changed: 24 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -4015,6 +4015,28 @@ static int qm_set_vf_mse(struct hisi_qm *qm, bool set)
40154015
return -ETIMEDOUT;
40164016
}
40174017

4018+
static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)
4019+
{
4020+
u32 nfe_enb = 0;
4021+
4022+
/* Kunpeng930 hardware automatically close master ooo when NFE occurs */
4023+
if (qm->ver >= QM_HW_V3)
4024+
return;
4025+
4026+
if (!qm->err_status.is_dev_ecc_mbit &&
4027+
qm->err_status.is_qm_ecc_mbit &&
4028+
qm->err_ini->close_axi_master_ooo) {
4029+
qm->err_ini->close_axi_master_ooo(qm);
4030+
} else if (qm->err_status.is_dev_ecc_mbit &&
4031+
!qm->err_status.is_qm_ecc_mbit &&
4032+
!qm->err_ini->close_axi_master_ooo) {
4033+
nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
4034+
writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,
4035+
qm->io_base + QM_RAS_NFE_ENABLE);
4036+
writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
4037+
}
4038+
}
4039+
40184040
static int qm_vf_reset_prepare(struct hisi_qm *qm,
40194041
enum qm_stop_reason stop_reason)
40204042
{
@@ -4079,6 +4101,8 @@ static int qm_controller_reset_prepare(struct hisi_qm *qm)
40794101
return ret;
40804102
}
40814103

4104+
qm_dev_ecc_mbit_handle(qm);
4105+
40824106
/* PF obtains the information of VF by querying the register. */
40834107
qm_cmd_uninit(qm);
40844108

@@ -4125,28 +4149,6 @@ static int qm_master_ooo_check(struct hisi_qm *qm)
41254149
return ret;
41264150
}
41274151

4128-
static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)
4129-
{
4130-
u32 nfe_enb = 0;
4131-
4132-
/* Kunpeng930 hardware automatically close master ooo when NFE occurs */
4133-
if (qm->ver >= QM_HW_V3)
4134-
return;
4135-
4136-
if (!qm->err_status.is_dev_ecc_mbit &&
4137-
qm->err_status.is_qm_ecc_mbit &&
4138-
qm->err_ini->close_axi_master_ooo) {
4139-
qm->err_ini->close_axi_master_ooo(qm);
4140-
} else if (qm->err_status.is_dev_ecc_mbit &&
4141-
!qm->err_status.is_qm_ecc_mbit &&
4142-
!qm->err_ini->close_axi_master_ooo) {
4143-
nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
4144-
writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,
4145-
qm->io_base + QM_RAS_NFE_ENABLE);
4146-
writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
4147-
}
4148-
}
4149-
41504152
static int qm_soft_reset_prepare(struct hisi_qm *qm)
41514153
{
41524154
struct pci_dev *pdev = qm->pdev;
@@ -4171,7 +4173,6 @@ static int qm_soft_reset_prepare(struct hisi_qm *qm)
41714173
return ret;
41724174
}
41734175

4174-
qm_dev_ecc_mbit_handle(qm);
41754176
ret = qm_master_ooo_check(qm);
41764177
if (ret)
41774178
return ret;

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