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Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux
Pull RISC-V updates from Palmer Dabbelt: "This contains an assortment of RISC-V related patches that I'd like to target for the 5.2 merge window. Most of the patches are cleanups, but there are a handful of user-visible changes: - The nosmp and nr_cpus command-line arguments are now supported, which work like normal. - The SBI console no longer installs itself as a preferred console, we rely on standard mechanisms (/chosen, command-line, hueristics) instead. - sfence_remove_sfence_vma{,_asid} now pass their arguments along to the SBI call. - Modules now support BUG(). - A missing sfence.vma during boot has been added. This bug only manifests during boot. - The arch/riscv support for SiFive's L2 cache controller has been merged, which should un-block the EDAC framework work. I've only tested this on QEMU again, as I didn't have time to get things running on the Unleashed. The latest master from this morning merges in cleanly and passes the tests as well" * tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: (31 commits) riscv: fix locking violation in page fault handler RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs RISC-V: Add DT documentation for SiFive L2 Cache Controller RISC-V: Avoid using invalid intermediate translations riscv: Support BUG() in kernel module riscv: Add the support for c.ebreak check in is_valid_bugaddr() riscv: support trap-based WARN() riscv: fix sbi_remote_sfence_vma{,_asid}. riscv: move switch_mm to its own file riscv: move flush_icache_{all,mm} to cacheflush.c tty: Don't force RISCV SBI console as preferred console RISC-V: Access CSRs using CSR numbers RISC-V: Add interrupt related SCAUSE defines in asm/csr.h RISC-V: Use tabs to align macro values in asm/csr.h RISC-V: Fix minor checkpatch issues. RISC-V: Support nr_cpus command line option. RISC-V: Implement nosmp commandline option. RISC-V: Add RISC-V specific arch_match_cpu_phys_id riscv: vdso: drop unnecessary cc-ldoption riscv: call pm_power_off from machine_halt / machine_power_off ...
2 parents 72cf0b0 + 8fef990 commit b0bb126

36 files changed

+635
-321
lines changed

‎Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
SiFive L2 Cache Controller
2+
--------------------------
3+
The SiFive Level 2 Cache Controller is used to provide access to fast copies
4+
of memory for masters in a Core Complex. The Level 2 Cache Controller also
5+
acts as directory-based coherency manager.
6+
All the properties in ePAPR/DeviceTree specification applies for this platform
7+
8+
Required Properties:
9+
--------------------
10+
- compatible: Should be "sifive,fu540-c000-ccache" and "cache"
11+
12+
- cache-block-size: Specifies the block size in bytes of the cache.
13+
Should be 64
14+
15+
- cache-level: Should be set to 2 for a level 2 cache
16+
17+
- cache-sets: Specifies the number of associativity sets of the cache.
18+
Should be 1024
19+
20+
- cache-size: Specifies the size in bytes of the cache. Should be 2097152
21+
22+
- cache-unified: Specifies the cache is a unified cache
23+
24+
- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals)
25+
26+
- reg: Physical base address and size of L2 cache controller registers map
27+
28+
Optional Properties:
29+
--------------------
30+
- next-level-cache: phandle to the next level cache if present.
31+
32+
- memory-region: reference to the reserved-memory for the L2 Loosely Integrated
33+
Memory region. The reserved memory node should be defined as per the bindings
34+
in reserved-memory.txt
35+
36+
37+
Example:
38+
39+
cache-controller@2010000 {
40+
compatible = "sifive,fu540-c000-ccache", "cache";
41+
cache-block-size = <64>;
42+
cache-level = <2>;
43+
cache-sets = <1024>;
44+
cache-size = <2097152>;
45+
cache-unified;
46+
interrupt-parent = <&plic0>;
47+
interrupts = <1 2 3>;
48+
reg = <0x0 0x2010000 0x0 0x1000>;
49+
next-level-cache = <&L25 &L40 &L36>;
50+
memory-region = <&l2_lim>;
51+
};

‎arch/riscv/Kconfig

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -27,15 +27,14 @@ config RISCV
2727
select GENERIC_STRNCPY_FROM_USER
2828
select GENERIC_STRNLEN_USER
2929
select GENERIC_SMP_IDLE_THREAD
30-
select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A
30+
select GENERIC_ATOMIC64 if !64BIT
3131
select HAVE_ARCH_AUDITSYSCALL
3232
select HAVE_MEMBLOCK_NODE_MAP
3333
select HAVE_DMA_CONTIGUOUS
3434
select HAVE_FUTEX_CMPXCHG if FUTEX
3535
select HAVE_PERF_EVENTS
3636
select HAVE_SYSCALL_TRACEPOINTS
3737
select IRQ_DOMAIN
38-
select RISCV_ISA_A if SMP
3938
select SPARSE_IRQ
4039
select SYSCTL_EXCEPTION_TRACE
4140
select HAVE_ARCH_TRACEHOOK
@@ -195,9 +194,6 @@ config RISCV_ISA_C
195194

196195
If you don't know what to do here, say Y.
197196

198-
config RISCV_ISA_A
199-
def_bool y
200-
201197
menu "supported PMU type"
202198
depends on PERF_EVENTS
203199

‎arch/riscv/Makefile

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Original file line numberDiff line numberDiff line change
@@ -39,9 +39,8 @@ endif
3939
KBUILD_CFLAGS += -Wall
4040

4141
# ISA string setting
42-
riscv-march-$(CONFIG_ARCH_RV32I) := rv32im
43-
riscv-march-$(CONFIG_ARCH_RV64I) := rv64im
44-
riscv-march-$(CONFIG_RISCV_ISA_A) := $(riscv-march-y)a
42+
riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
43+
riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
4544
riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
4645
riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
4746
KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))

‎arch/riscv/include/asm/Kbuild

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Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@ generic-y += compat.h
44
generic-y += cputime.h
55
generic-y += device.h
66
generic-y += div64.h
7+
generic-y += extable.h
78
generic-y += dma.h
89
generic-y += dma-contiguous.h
910
generic-y += dma-mapping.h

‎arch/riscv/include/asm/bug.h

Lines changed: 24 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,12 @@
2121
#include <asm/asm.h>
2222

2323
#ifdef CONFIG_GENERIC_BUG
24-
#define __BUG_INSN _AC(0x00100073, UL) /* ebreak */
24+
#define __INSN_LENGTH_MASK _UL(0x3)
25+
#define __INSN_LENGTH_32 _UL(0x3)
26+
#define __COMPRESSED_INSN_MASK _UL(0xffff)
27+
28+
#define __BUG_INSN_32 _UL(0x00100073) /* ebreak */
29+
#define __BUG_INSN_16 _UL(0x9002) /* c.ebreak */
2530

2631
#ifndef __ASSEMBLY__
2732
typedef u32 bug_insn_t;
@@ -38,38 +43,46 @@ typedef u32 bug_insn_t;
3843
#define __BUG_ENTRY \
3944
__BUG_ENTRY_ADDR "\n\t" \
4045
__BUG_ENTRY_FILE "\n\t" \
41-
RISCV_SHORT " %1"
46+
RISCV_SHORT " %1\n\t" \
47+
RISCV_SHORT " %2"
4248
#else
4349
#define __BUG_ENTRY \
44-
__BUG_ENTRY_ADDR
50+
__BUG_ENTRY_ADDR "\n\t" \
51+
RISCV_SHORT " %2"
4552
#endif
4653

47-
#define BUG() \
54+
#define __BUG_FLAGS(flags) \
4855
do { \
4956
__asm__ __volatile__ ( \
5057
"1:\n\t" \
5158
"ebreak\n" \
52-
".pushsection __bug_table,\"a\"\n\t" \
59+
".pushsection __bug_table,\"aw\"\n\t" \
5360
"2:\n\t" \
5461
__BUG_ENTRY "\n\t" \
55-
".org 2b + %2\n\t" \
62+
".org 2b + %3\n\t" \
5663
".popsection" \
5764
: \
5865
: "i" (__FILE__), "i" (__LINE__), \
59-
"i" (sizeof(struct bug_entry))); \
60-
unreachable(); \
66+
"i" (flags), \
67+
"i" (sizeof(struct bug_entry))); \
6168
} while (0)
69+
6270
#endif /* !__ASSEMBLY__ */
6371
#else /* CONFIG_GENERIC_BUG */
6472
#ifndef __ASSEMBLY__
65-
#define BUG() \
66-
do { \
73+
#define __BUG_FLAGS(flags) do { \
6774
__asm__ __volatile__ ("ebreak\n"); \
68-
unreachable(); \
6975
} while (0)
7076
#endif /* !__ASSEMBLY__ */
7177
#endif /* CONFIG_GENERIC_BUG */
7278

79+
#define BUG() do { \
80+
__BUG_FLAGS(0); \
81+
unreachable(); \
82+
} while (0)
83+
84+
#define __WARN_FLAGS(flags) __BUG_FLAGS(BUGFLAG_WARNING|(flags))
85+
7386
#define HAVE_ARCH_BUG
7487

7588
#include <asm-generic/bug.h>

‎arch/riscv/include/asm/cacheflush.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ static inline void flush_dcache_page(struct page *page)
4747

4848
#else /* CONFIG_SMP */
4949

50-
#define flush_icache_all() sbi_remote_fence_i(NULL)
50+
void flush_icache_all(void);
5151
void flush_icache_mm(struct mm_struct *mm, bool local);
5252

5353
#endif /* CONFIG_SMP */

‎arch/riscv/include/asm/csr.h

Lines changed: 77 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -14,64 +14,95 @@
1414
#ifndef _ASM_RISCV_CSR_H
1515
#define _ASM_RISCV_CSR_H
1616

17+
#include <asm/asm.h>
1718
#include <linux/const.h>
1819

1920
/* Status register flags */
20-
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
21-
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
22-
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
23-
#define SR_SUM _AC(0x00040000, UL) /* Supervisor may access User Memory */
24-
25-
#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
26-
#define SR_FS_OFF _AC(0x00000000, UL)
27-
#define SR_FS_INITIAL _AC(0x00002000, UL)
28-
#define SR_FS_CLEAN _AC(0x00004000, UL)
29-
#define SR_FS_DIRTY _AC(0x00006000, UL)
30-
31-
#define SR_XS _AC(0x00018000, UL) /* Extension Status */
32-
#define SR_XS_OFF _AC(0x00000000, UL)
33-
#define SR_XS_INITIAL _AC(0x00008000, UL)
34-
#define SR_XS_CLEAN _AC(0x00010000, UL)
35-
#define SR_XS_DIRTY _AC(0x00018000, UL)
21+
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
22+
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
23+
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
24+
#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
25+
26+
#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
27+
#define SR_FS_OFF _AC(0x00000000, UL)
28+
#define SR_FS_INITIAL _AC(0x00002000, UL)
29+
#define SR_FS_CLEAN _AC(0x00004000, UL)
30+
#define SR_FS_DIRTY _AC(0x00006000, UL)
31+
32+
#define SR_XS _AC(0x00018000, UL) /* Extension Status */
33+
#define SR_XS_OFF _AC(0x00000000, UL)
34+
#define SR_XS_INITIAL _AC(0x00008000, UL)
35+
#define SR_XS_CLEAN _AC(0x00010000, UL)
36+
#define SR_XS_DIRTY _AC(0x00018000, UL)
3637

3738
#ifndef CONFIG_64BIT
38-
#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
39+
#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
3940
#else
40-
#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
41+
#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
4142
#endif
4243

4344
/* SATP flags */
44-
#if __riscv_xlen == 32
45-
#define SATP_PPN _AC(0x003FFFFF, UL)
46-
#define SATP_MODE_32 _AC(0x80000000, UL)
47-
#define SATP_MODE SATP_MODE_32
45+
#ifndef CONFIG_64BIT
46+
#define SATP_PPN _AC(0x003FFFFF, UL)
47+
#define SATP_MODE_32 _AC(0x80000000, UL)
48+
#define SATP_MODE SATP_MODE_32
4849
#else
49-
#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
50-
#define SATP_MODE_39 _AC(0x8000000000000000, UL)
51-
#define SATP_MODE SATP_MODE_39
50+
#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
51+
#define SATP_MODE_39 _AC(0x8000000000000000, UL)
52+
#define SATP_MODE SATP_MODE_39
5253
#endif
5354

54-
/* Interrupt Enable and Interrupt Pending flags */
55-
#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */
56-
#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */
57-
#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */
58-
59-
#define EXC_INST_MISALIGNED 0
60-
#define EXC_INST_ACCESS 1
61-
#define EXC_BREAKPOINT 3
62-
#define EXC_LOAD_ACCESS 5
63-
#define EXC_STORE_ACCESS 7
64-
#define EXC_SYSCALL 8
65-
#define EXC_INST_PAGE_FAULT 12
66-
#define EXC_LOAD_PAGE_FAULT 13
67-
#define EXC_STORE_PAGE_FAULT 15
55+
/* SCAUSE */
56+
#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
57+
58+
#define IRQ_U_SOFT 0
59+
#define IRQ_S_SOFT 1
60+
#define IRQ_M_SOFT 3
61+
#define IRQ_U_TIMER 4
62+
#define IRQ_S_TIMER 5
63+
#define IRQ_M_TIMER 7
64+
#define IRQ_U_EXT 8
65+
#define IRQ_S_EXT 9
66+
#define IRQ_M_EXT 11
67+
68+
#define EXC_INST_MISALIGNED 0
69+
#define EXC_INST_ACCESS 1
70+
#define EXC_BREAKPOINT 3
71+
#define EXC_LOAD_ACCESS 5
72+
#define EXC_STORE_ACCESS 7
73+
#define EXC_SYSCALL 8
74+
#define EXC_INST_PAGE_FAULT 12
75+
#define EXC_LOAD_PAGE_FAULT 13
76+
#define EXC_STORE_PAGE_FAULT 15
77+
78+
/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
79+
#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
80+
#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER)
81+
#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT)
82+
83+
#define CSR_CYCLE 0xc00
84+
#define CSR_TIME 0xc01
85+
#define CSR_INSTRET 0xc02
86+
#define CSR_SSTATUS 0x100
87+
#define CSR_SIE 0x104
88+
#define CSR_STVEC 0x105
89+
#define CSR_SCOUNTEREN 0x106
90+
#define CSR_SSCRATCH 0x140
91+
#define CSR_SEPC 0x141
92+
#define CSR_SCAUSE 0x142
93+
#define CSR_STVAL 0x143
94+
#define CSR_SIP 0x144
95+
#define CSR_SATP 0x180
96+
#define CSR_CYCLEH 0xc80
97+
#define CSR_TIMEH 0xc81
98+
#define CSR_INSTRETH 0xc82
6899

69100
#ifndef __ASSEMBLY__
70101

71102
#define csr_swap(csr, val) \
72103
({ \
73104
unsigned long __v = (unsigned long)(val); \
74-
__asm__ __volatile__ ("csrrw %0, " #csr ", %1" \
105+
__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
75106
: "=r" (__v) : "rK" (__v) \
76107
: "memory"); \
77108
__v; \
@@ -80,7 +111,7 @@
80111
#define csr_read(csr) \
81112
({ \
82113
register unsigned long __v; \
83-
__asm__ __volatile__ ("csrr %0, " #csr \
114+
__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
84115
: "=r" (__v) : \
85116
: "memory"); \
86117
__v; \
@@ -89,15 +120,15 @@
89120
#define csr_write(csr, val) \
90121
({ \
91122
unsigned long __v = (unsigned long)(val); \
92-
__asm__ __volatile__ ("csrw " #csr ", %0" \
123+
__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
93124
: : "rK" (__v) \
94125
: "memory"); \
95126
})
96127

97128
#define csr_read_set(csr, val) \
98129
({ \
99130
unsigned long __v = (unsigned long)(val); \
100-
__asm__ __volatile__ ("csrrs %0, " #csr ", %1" \
131+
__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
101132
: "=r" (__v) : "rK" (__v) \
102133
: "memory"); \
103134
__v; \
@@ -106,15 +137,15 @@
106137
#define csr_set(csr, val) \
107138
({ \
108139
unsigned long __v = (unsigned long)(val); \
109-
__asm__ __volatile__ ("csrs " #csr ", %0" \
140+
__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
110141
: : "rK" (__v) \
111142
: "memory"); \
112143
})
113144

114145
#define csr_read_clear(csr, val) \
115146
({ \
116147
unsigned long __v = (unsigned long)(val); \
117-
__asm__ __volatile__ ("csrrc %0, " #csr ", %1" \
148+
__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
118149
: "=r" (__v) : "rK" (__v) \
119150
: "memory"); \
120151
__v; \
@@ -123,7 +154,7 @@
123154
#define csr_clear(csr, val) \
124155
({ \
125156
unsigned long __v = (unsigned long)(val); \
126-
__asm__ __volatile__ ("csrc " #csr ", %0" \
157+
__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
127158
: : "rK" (__v) \
128159
: "memory"); \
129160
})

‎arch/riscv/include/asm/elf.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -27,13 +27,7 @@
2727
#define ELF_CLASS ELFCLASS32
2828
#endif
2929

30-
#if defined(__LITTLE_ENDIAN)
3130
#define ELF_DATA ELFDATA2LSB
32-
#elif defined(__BIG_ENDIAN)
33-
#define ELF_DATA ELFDATA2MSB
34-
#else
35-
#error "Unknown endianness"
36-
#endif
3731

3832
/*
3933
* This is used to ensure we don't load something for the wrong architecture.

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