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joergroedeljoergroedel
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Merge branches 'apple/dart', 'arm/mediatek', 'arm/msm', 'arm/smmu', 'ppc/pamu', 'x86/vt-d', 'x86/amd' and 'vfio-notifier-fix' into next
8 parents ee53543 + de78657 + 8b9ad48 + b11deb2 + cae8d1f + 0d647b3 + 42bb5aa + fa7e9ec commit b0dacee

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‎.mailmap

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@@ -45,6 +45,7 @@ Andrey Konovalov <[email protected]> <[email protected]>
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Andrey Ryabinin <[email protected]> <[email protected]>
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Andrey Ryabinin <[email protected]> <[email protected]>
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Andrzej Hajda <[email protected]> <[email protected]>
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André Almeida <[email protected]> <[email protected]>
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Andy Adamson <[email protected]>
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Antoine Tenart <[email protected]> <[email protected]>
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Antoine Tenart <[email protected]> <[email protected]>
@@ -204,6 +205,7 @@ Juha Yrjola <at solidboot.com>
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Juha Yrjola <[email protected]>
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Juha Yrjola <[email protected]>
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Julien Thierry <[email protected]> <[email protected]>
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Kalle Valo <[email protected]> <[email protected]>
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Kalyan Thota <[email protected]> <[email protected]>
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Kay Sievers <[email protected]>
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Kees Cook <[email protected]> <[email protected]>
@@ -249,6 +251,7 @@ Mark Yao <[email protected]> <[email protected]>
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Martin Kepplinger <[email protected]> <[email protected]>
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Martin Kepplinger <[email protected]> <[email protected]>
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Martin Kepplinger <[email protected]> <[email protected]>
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Martyna Szapar-Mudlaw <[email protected]> <[email protected]>
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Mathieu Othacehe <[email protected]>
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Matthew Wilcox <[email protected]> <[email protected]>
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Matthew Wilcox <[email protected]> <[email protected]>

‎Documentation/arm64/memory-tagging-extension.rst

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@@ -228,10 +228,10 @@ Core dump support
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-----------------
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The allocation tags for user memory mapped with ``PROT_MTE`` are dumped
231-
in the core file as additional ``PT_ARM_MEMTAG_MTE`` segments. The
231+
in the core file as additional ``PT_AARCH64_MEMTAG_MTE`` segments. The
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program header for such segment is defined as:
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234-
:``p_type``: ``PT_ARM_MEMTAG_MTE``
234+
:``p_type``: ``PT_AARCH64_MEMTAG_MTE``
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:``p_flags``: 0
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:``p_offset``: segment file offset
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:``p_vaddr``: segment virtual address, same as the corresponding

‎Documentation/arm64/silicon-errata.rst

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@@ -189,6 +189,9 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
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+----------------+-----------------+-----------------+-----------------------------+

‎Documentation/devicetree/bindings/clock/imx8m-clock.yaml

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Original file line numberDiff line numberDiff line change
@@ -55,8 +55,6 @@ allOf:
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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items:
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- description: 32k osc
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- description: 25m osc
@@ -66,8 +64,6 @@ allOf:
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- description: ext3 clock input
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- description: ext4 clock input
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clock-names:
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minItems: 7
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maxItems: 7
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items:
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- const: ckil
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- const: osc_25m

‎Documentation/devicetree/bindings/clock/microchip,mpfs.yaml

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@@ -22,7 +22,16 @@ properties:
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const: microchip,mpfs-clkcfg
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reg:
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maxItems: 1
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items:
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- description: |
27+
clock config registers:
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These registers contain enable, reset & divider tables for the, cpu,
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axi, ahb and rtc/mtimer reference clocks as well as enable and reset
30+
for the peripheral clocks.
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- description: |
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mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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clocks:
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maxItems: 1
@@ -51,7 +60,7 @@ examples:
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#size-cells = <2>;
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clkcfg: clock-controller@20002000 {
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compatible = "microchip,mpfs-clkcfg";
54-
reg = <0x0 0x20002000 0x0 0x1000>;
63+
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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clocks = <&ref>;
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#clock-cells = <1>;
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};

‎Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml

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properties:
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clocks:
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minItems: 1
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maxItems: 4
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items:
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- description: Functional clock
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- description: EXTAL input clock
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clock-names:
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minItems: 1
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maxItems: 4
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- const: fck
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# The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
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else:
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properties:
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clocks:
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maxItems: 1
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items:
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- description: Functional clock
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clock-names:
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maxItems: 1
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items:
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- const: fck
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‎Documentation/devicetree/bindings/display/renesas,du.yaml

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@@ -109,15 +109,13 @@ allOf:
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properties:
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clocks:
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minItems: 1
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maxItems: 3
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items:
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- description: Functional clock
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- description: DU_DOTCLKIN0 input clock
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- description: DU_DOTCLKIN1 input clock
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clock-names:
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minItems: 1
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maxItems: 3
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- const: du.0
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- pattern: '^dclkin\.[01]$'
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properties:
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clocks:
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maxItems: 4
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- description: Functional clock for DU0
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- description: Functional clock for DU1
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clock-names:
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minItems: 2
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maxItems: 4
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- const: du.0
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- const: du.1
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properties:
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- description: Functional clock for DU0
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- description: Functional clock for DU1
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- const: du.0
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- const: du.1
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- description: Functional clock for DU0
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- description: Functional clock for DU1
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- const: du.1
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- description: Functional clock for DU0
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- description: DU_DOTCLKIN0 input clock
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- const: du.0
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- description: Functional clock for DU0
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- description: Functional clock for DU1
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- const: du.0
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‎Documentation/devicetree/bindings/hwmon/ti,tmp421.yaml

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@@ -58,10 +58,9 @@ patternProperties:
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The value (two's complement) to be programmed in the channel specific N correction register.
6060
For remote channels only.
61-
$ref: /schemas/types.yaml#/definitions/uint32
62-
items:
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minimum: 0
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maximum: 255
61+
$ref: /schemas/types.yaml#/definitions/int32
62+
minimum: -128
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- reg

‎Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml

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- const: adc
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‎Documentation/devicetree/bindings/iommu/arm,smmu.yaml

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@@ -37,8 +37,10 @@ properties:
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- qcom,sc7180-smmu-500
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- qcom,sc7280-smmu-500
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- qcom,sc8180x-smmu-500
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- qcom,sc8280xp-smmu-500
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- qcom,sdm845-smmu-500
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- qcom,sdx55-smmu-500
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- qcom,sdx65-smmu-500
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- qcom,sm6350-smmu-500
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- qcom,sm8150-smmu-500
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- qcom,sm8250-smmu-500
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for improved performance.
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- enum:
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- nvidia,tegra194-smmu
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- nvidia,tegra186-smmu
68+
- nvidia,tegra194-smmu
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- nvidia,tegra234-smmu
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- const: nvidia,smmu-500
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- items:
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- const: arm,mmu-500
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power-domains:
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maxItems: 1
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163+
nvidia,memory-controller:
164+
description: |
165+
A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
166+
The memory controller needs to be programmed with a mapping of memory
167+
client IDs to ARM SMMU stream IDs.
168+
169+
If this property is absent, the mapping programmed by early firmware
170+
will be used and it is not guaranteed that IOMMU translations will be
171+
enabled for any given device.
172+
$ref: /schemas/types.yaml#/definitions/phandle
173+
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required:
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- compatible
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- reg
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compatible:
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contains:
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enum:
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- nvidia,tegra194-smmu
176189
- nvidia,tegra186-smmu
190+
- nvidia,tegra194-smmu
191+
- nvidia,tegra234-smmu
177192
then:
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properties:
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reg:
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minItems: 1
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maxItems: 2
197+
198+
# The reference to the memory controller is required to ensure that the
199+
# memory client to stream ID mapping can be done synchronously with the
200+
# IOMMU attachment.
201+
required:
202+
- nvidia,memory-controller
182203
else:
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properties:
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reg:

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