drm/xe: Mark ComputeCS read mode as UC on iGPU

RING_CMD_CCTL read index should be UC on iGPU parts due to L3 caching
structure. Having this as WB blocks ULLS from being enabled. Change to
UC to unblock ULLS on iGPU.

v2:
 - Drop internal communications commnet, bspec is updated

Cc: Balasubramani Vivekanandan <[email protected]>
Cc: Michal Mrozek <[email protected]>
Cc: Paulo Zanoni <[email protected]>
Cc: José Roberto de Souza <[email protected]>
Cc: [email protected]
Fixes: 328e089 ("drm/xe: Leverage ComputeCS read L3 caching")
Signed-off-by: Matthew Brost <[email protected]>
Acked-by: Michal Mrozek <[email protected]>
Reviewed-by: Stuart Summers <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 758debf)
Signed-off-by: Thomas Hellström <[email protected]>

Author: mbrost05

drivers/gpu/drm/xe/xe_hw_engine.c

@@ -419,7 +419,7 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
 	 * Bspec: 72161
 	 */
 	const u8 mocs_write_idx = gt->mocs.uc_index;
-	const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE &&
+	const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
 				 (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?
 				 gt->mocs.wb_index : gt->mocs.uc_index;
 	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |