|
13 | 13 | struct wilc_spi {
|
14 | 14 | int crc_off;
|
15 | 15 | int nint;
|
16 |
| - int has_thrpt_enh; |
17 | 16 | };
|
18 | 17 |
|
19 | 18 | static const struct wilc_hif_func wilc_hif_spi;
|
@@ -897,163 +896,29 @@ static int wilc_spi_init(struct wilc *wilc, bool resume)
|
897 | 896 | return 0;
|
898 | 897 | }
|
899 | 898 |
|
900 |
| - spi_priv->has_thrpt_enh = 1; |
901 |
| - |
902 | 899 | isinit = 1;
|
903 | 900 |
|
904 | 901 | return 1;
|
905 | 902 | }
|
906 | 903 |
|
907 | 904 | static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
|
908 | 905 | {
|
909 |
| - struct spi_device *spi = to_spi_device(wilc->dev); |
910 |
| - struct wilc_spi *spi_priv = wilc->bus_data; |
911 | 906 | int ret;
|
912 | 907 |
|
913 |
| - if (spi_priv->has_thrpt_enh) { |
914 |
| - ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, |
915 |
| - size); |
916 |
| - *size = *size & IRQ_DMA_WD_CNT_MASK; |
917 |
| - } else { |
918 |
| - u32 tmp; |
919 |
| - u32 byte_cnt; |
920 |
| - |
921 |
| - ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, |
922 |
| - &byte_cnt); |
923 |
| - if (!ret) { |
924 |
| - dev_err(&spi->dev, |
925 |
| - "Failed read WILC_VMM_TO_HOST_SIZE ...\n"); |
926 |
| - return ret; |
927 |
| - } |
928 |
| - tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK; |
929 |
| - *size = tmp; |
930 |
| - } |
| 908 | + ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, size); |
| 909 | + *size = *size & IRQ_DMA_WD_CNT_MASK; |
931 | 910 |
|
932 | 911 | return ret;
|
933 | 912 | }
|
934 | 913 |
|
935 | 914 | static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
|
936 | 915 | {
|
937 |
| - struct spi_device *spi = to_spi_device(wilc->dev); |
938 |
| - struct wilc_spi *spi_priv = wilc->bus_data; |
939 |
| - int ret; |
940 |
| - u32 tmp; |
941 |
| - u32 byte_cnt; |
942 |
| - bool unexpected_irq; |
943 |
| - int j; |
944 |
| - u32 unknown_mask; |
945 |
| - u32 irq_flags; |
946 |
| - int k = IRG_FLAGS_OFFSET + 5; |
947 |
| - |
948 |
| - if (spi_priv->has_thrpt_enh) |
949 |
| - return spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, |
950 |
| - int_status); |
951 |
| - ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, &byte_cnt); |
952 |
| - if (!ret) { |
953 |
| - dev_err(&spi->dev, |
954 |
| - "Failed read WILC_VMM_TO_HOST_SIZE ...\n"); |
955 |
| - return ret; |
956 |
| - } |
957 |
| - tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK; |
958 |
| - |
959 |
| - j = 0; |
960 |
| - do { |
961 |
| - wilc_spi_read_reg(wilc, 0x1a90, &irq_flags); |
962 |
| - tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET); |
963 |
| - |
964 |
| - if (spi_priv->nint > 5) { |
965 |
| - wilc_spi_read_reg(wilc, 0x1a94, &irq_flags); |
966 |
| - tmp |= (((irq_flags >> 0) & 0x7) << k); |
967 |
| - } |
968 |
| - |
969 |
| - unknown_mask = ~((1ul << spi_priv->nint) - 1); |
970 |
| - |
971 |
| - unexpected_irq = (tmp >> IRG_FLAGS_OFFSET) & unknown_mask; |
972 |
| - if (unexpected_irq) { |
973 |
| - dev_err(&spi->dev, |
974 |
| - "Unexpected interrupt(2):j=%d,tmp=%x,mask=%x\n", |
975 |
| - j, tmp, unknown_mask); |
976 |
| - } |
977 |
| - |
978 |
| - j++; |
979 |
| - } while (unexpected_irq); |
980 |
| - |
981 |
| - *int_status = tmp; |
982 |
| - |
983 |
| - return ret; |
| 916 | + return spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, int_status); |
984 | 917 | }
|
985 | 918 |
|
986 | 919 | static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
|
987 | 920 | {
|
988 |
| - struct spi_device *spi = to_spi_device(wilc->dev); |
989 |
| - struct wilc_spi *spi_priv = wilc->bus_data; |
990 |
| - int ret; |
991 |
| - u32 flags; |
992 |
| - u32 tbl_ctl; |
993 |
| - |
994 |
| - if (spi_priv->has_thrpt_enh) { |
995 |
| - return spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE, |
996 |
| - val); |
997 |
| - } |
998 |
| - |
999 |
| - flags = val & (BIT(MAX_NUM_INT) - 1); |
1000 |
| - if (flags) { |
1001 |
| - int i; |
1002 |
| - |
1003 |
| - ret = 1; |
1004 |
| - for (i = 0; i < spi_priv->nint; i++) { |
1005 |
| - /* |
1006 |
| - * No matter what you write 1 or 0, |
1007 |
| - * it will clear interrupt. |
1008 |
| - */ |
1009 |
| - if (flags & 1) |
1010 |
| - ret = wilc_spi_write_reg(wilc, |
1011 |
| - 0x10c8 + i * 4, 1); |
1012 |
| - if (!ret) |
1013 |
| - break; |
1014 |
| - flags >>= 1; |
1015 |
| - } |
1016 |
| - if (!ret) { |
1017 |
| - dev_err(&spi->dev, |
1018 |
| - "Failed wilc_spi_write_reg, set reg %x ...\n", |
1019 |
| - 0x10c8 + i * 4); |
1020 |
| - return ret; |
1021 |
| - } |
1022 |
| - for (i = spi_priv->nint; i < MAX_NUM_INT; i++) { |
1023 |
| - if (flags & 1) |
1024 |
| - dev_err(&spi->dev, |
1025 |
| - "Unexpected interrupt cleared %d...\n", |
1026 |
| - i); |
1027 |
| - flags >>= 1; |
1028 |
| - } |
1029 |
| - } |
1030 |
| - |
1031 |
| - tbl_ctl = 0; |
1032 |
| - /* select VMM table 0 */ |
1033 |
| - if (val & SEL_VMM_TBL0) |
1034 |
| - tbl_ctl |= BIT(0); |
1035 |
| - /* select VMM table 1 */ |
1036 |
| - if (val & SEL_VMM_TBL1) |
1037 |
| - tbl_ctl |= BIT(1); |
1038 |
| - |
1039 |
| - ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL, tbl_ctl); |
1040 |
| - if (!ret) { |
1041 |
| - dev_err(&spi->dev, "fail write reg vmm_tbl_ctl...\n"); |
1042 |
| - return ret; |
1043 |
| - } |
1044 |
| - |
1045 |
| - if (val & EN_VMM) { |
1046 |
| - /* |
1047 |
| - * enable vmm transfer. |
1048 |
| - */ |
1049 |
| - ret = wilc_spi_write_reg(wilc, WILC_VMM_CORE_CTL, 1); |
1050 |
| - if (!ret) { |
1051 |
| - dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n"); |
1052 |
| - return ret; |
1053 |
| - } |
1054 |
| - } |
1055 |
| - |
1056 |
| - return ret; |
| 921 | + return spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE, val); |
1057 | 922 | }
|
1058 | 923 |
|
1059 | 924 | static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
|
|
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