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hegdevasantjoergroedel
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iommu/amd: Rearrange GCR3 table setup code
Consolidate GCR3 table related code in one place so that its easy to maintain. Note that this patch doesn't move __set_gcr3/__clear_gcr3. We are moving GCR3 table from per domain to per device. Following series will rework these functions. During that time I will move these functions as well. No functional changes intended. Signed-off-by: Vasant Hegde <[email protected]> Reviewed-by: Jason Gunthorpe <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
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drivers/iommu/amd/iommu.c

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1714,6 +1714,38 @@ static int setup_gcr3_table(struct protection_domain *domain, int pasids)
17141714
return 0;
17151715
}
17161716

1717+
static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
1718+
{
1719+
int index;
1720+
u64 *pte;
1721+
1722+
while (true) {
1723+
1724+
index = (pasid >> (9 * level)) & 0x1ff;
1725+
pte = &root[index];
1726+
1727+
if (level == 0)
1728+
break;
1729+
1730+
if (!(*pte & GCR3_VALID)) {
1731+
if (!alloc)
1732+
return NULL;
1733+
1734+
root = (void *)get_zeroed_page(GFP_ATOMIC);
1735+
if (root == NULL)
1736+
return NULL;
1737+
1738+
*pte = iommu_virt_to_phys(root) | GCR3_VALID;
1739+
}
1740+
1741+
root = iommu_phys_to_virt(*pte & PAGE_MASK);
1742+
1743+
level -= 1;
1744+
}
1745+
1746+
return pte;
1747+
}
1748+
17171749
static void set_dte_entry(struct amd_iommu *iommu,
17181750
struct iommu_dev_data *dev_data)
17191751
{
@@ -2737,38 +2769,6 @@ int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
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return ret;
27382770
}
27392771

2740-
static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2741-
{
2742-
int index;
2743-
u64 *pte;
2744-
2745-
while (true) {
2746-
2747-
index = (pasid >> (9 * level)) & 0x1ff;
2748-
pte = &root[index];
2749-
2750-
if (level == 0)
2751-
break;
2752-
2753-
if (!(*pte & GCR3_VALID)) {
2754-
if (!alloc)
2755-
return NULL;
2756-
2757-
root = (void *)get_zeroed_page(GFP_ATOMIC);
2758-
if (root == NULL)
2759-
return NULL;
2760-
2761-
*pte = iommu_virt_to_phys(root) | GCR3_VALID;
2762-
}
2763-
2764-
root = iommu_phys_to_virt(*pte & PAGE_MASK);
2765-
2766-
level -= 1;
2767-
}
2768-
2769-
return pte;
2770-
}
2771-
27722772
static int __set_gcr3(struct protection_domain *domain, u32 pasid,
27732773
unsigned long cr3)
27742774
{

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