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crypto: riscv - add vector crypto accelerated SHA-{512,384}
Add an implementation of SHA-512 and SHA-384 using the Zvknhb extension. The assembly code is derived from OpenSSL code (openssl/openssl#21923) that was dual-licensed so that it could be reused in the kernel. Nevertheless, the assembly has been significantly reworked for integration with the kernel, for example by using a regular .S file instead of the so-called perlasm, using the assembler instead of bare '.inst', and greatly reducing code duplication. Co-developed-by: Charalampos Mitrodimas <[email protected]> Signed-off-by: Charalampos Mitrodimas <[email protected]> Co-developed-by: Heiko Stuebner <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Co-developed-by: Phoebe Chen <[email protected]> Signed-off-by: Phoebe Chen <[email protected]> Signed-off-by: Jerry Shih <[email protected]> Co-developed-by: Eric Biggers <[email protected]> Signed-off-by: Eric Biggers <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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‎arch/riscv/crypto/Kconfig

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@@ -50,4 +50,15 @@ config CRYPTO_SHA256_RISCV64
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- Zvknha or Zvknhb vector crypto extensions
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- Zvkb vector crypto extension
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config CRYPTO_SHA512_RISCV64
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tristate "Hash functions: SHA-384 and SHA-512"
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depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
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select CRYPTO_SHA512
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help
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SHA-384 and SHA-512 secure hash algorithm (FIPS 180)
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Architecture: riscv64 using:
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- Zvknhb vector crypto extension
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- Zvkb vector crypto extension
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5364
endmenu

‎arch/riscv/crypto/Makefile

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@@ -12,3 +12,6 @@ ghash-riscv64-y := ghash-riscv64-glue.o ghash-riscv64-zvkg.o
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obj-$(CONFIG_CRYPTO_SHA256_RISCV64) += sha256-riscv64.o
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sha256-riscv64-y := sha256-riscv64-glue.o sha256-riscv64-zvknha_or_zvknhb-zvkb.o
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obj-$(CONFIG_CRYPTO_SHA512_RISCV64) += sha512-riscv64.o
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sha512-riscv64-y := sha512-riscv64-glue.o sha512-riscv64-zvknhb-zvkb.o

‎arch/riscv/crypto/sha512-riscv64-glue.c

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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* SHA-512 and SHA-384 using the RISC-V vector crypto extensions
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*
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* Copyright (C) 2023 VRULL GmbH
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* Author: Heiko Stuebner <[email protected]>
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*
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* Copyright (C) 2023 SiFive, Inc.
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* Author: Jerry Shih <[email protected]>
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*/
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#include <asm/simd.h>
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#include <asm/vector.h>
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#include <crypto/internal/hash.h>
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#include <crypto/internal/simd.h>
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#include <crypto/sha512_base.h>
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#include <linux/linkage.h>
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#include <linux/module.h>
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/*
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* Note: the asm function only uses the 'state' field of struct sha512_state.
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* It is assumed to be the first field.
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*/
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asmlinkage void sha512_transform_zvknhb_zvkb(
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struct sha512_state *state, const u8 *data, int num_blocks);
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static int riscv64_sha512_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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/*
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* Ensure struct sha512_state begins directly with the SHA-512
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* 512-bit internal state, as this is what the asm function expects.
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*/
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BUILD_BUG_ON(offsetof(struct sha512_state, state) != 0);
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if (crypto_simd_usable()) {
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kernel_vector_begin();
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sha512_base_do_update(desc, data, len,
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sha512_transform_zvknhb_zvkb);
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kernel_vector_end();
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} else {
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crypto_sha512_update(desc, data, len);
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}
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return 0;
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}
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static int riscv64_sha512_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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if (crypto_simd_usable()) {
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kernel_vector_begin();
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if (len)
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sha512_base_do_update(desc, data, len,
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sha512_transform_zvknhb_zvkb);
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sha512_base_do_finalize(desc, sha512_transform_zvknhb_zvkb);
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kernel_vector_end();
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return sha512_base_finish(desc, out);
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}
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return crypto_sha512_finup(desc, data, len, out);
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}
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static int riscv64_sha512_final(struct shash_desc *desc, u8 *out)
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{
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return riscv64_sha512_finup(desc, NULL, 0, out);
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}
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static int riscv64_sha512_digest(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return sha512_base_init(desc) ?:
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riscv64_sha512_finup(desc, data, len, out);
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}
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static struct shash_alg riscv64_sha512_algs[] = {
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{
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.init = sha512_base_init,
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.update = riscv64_sha512_update,
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.final = riscv64_sha512_final,
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.finup = riscv64_sha512_finup,
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.digest = riscv64_sha512_digest,
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.descsize = sizeof(struct sha512_state),
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.digestsize = SHA512_DIGEST_SIZE,
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.base = {
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.cra_blocksize = SHA512_BLOCK_SIZE,
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.cra_priority = 300,
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.cra_name = "sha512",
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.cra_driver_name = "sha512-riscv64-zvknhb-zvkb",
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.cra_module = THIS_MODULE,
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},
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}, {
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.init = sha384_base_init,
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.update = riscv64_sha512_update,
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.final = riscv64_sha512_final,
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.finup = riscv64_sha512_finup,
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.descsize = sizeof(struct sha512_state),
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.digestsize = SHA384_DIGEST_SIZE,
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.base = {
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.cra_blocksize = SHA384_BLOCK_SIZE,
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.cra_priority = 300,
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.cra_name = "sha384",
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.cra_driver_name = "sha384-riscv64-zvknhb-zvkb",
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.cra_module = THIS_MODULE,
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},
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},
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};
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static int __init riscv64_sha512_mod_init(void)
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{
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if (riscv_isa_extension_available(NULL, ZVKNHB) &&
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riscv_isa_extension_available(NULL, ZVKB) &&
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riscv_vector_vlen() >= 128)
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return crypto_register_shashes(riscv64_sha512_algs,
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ARRAY_SIZE(riscv64_sha512_algs));
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return -ENODEV;
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}
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static void __exit riscv64_sha512_mod_exit(void)
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{
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crypto_unregister_shashes(riscv64_sha512_algs,
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ARRAY_SIZE(riscv64_sha512_algs));
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}
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module_init(riscv64_sha512_mod_init);
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module_exit(riscv64_sha512_mod_exit);
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MODULE_DESCRIPTION("SHA-512 (RISC-V accelerated)");
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MODULE_AUTHOR("Heiko Stuebner <[email protected]>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS_CRYPTO("sha512");
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MODULE_ALIAS_CRYPTO("sha384");

‎arch/riscv/crypto/sha512-riscv64-zvknhb-zvkb.S

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/* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
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//
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// This file is dual-licensed, meaning that you can use it under your
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// choice of either of the following two licenses:
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//
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// Copyright 2023 The OpenSSL Project Authors. All Rights Reserved.
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//
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// Licensed under the Apache License 2.0 (the "License"). You can obtain
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// a copy in the file LICENSE in the source distribution or at
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// https://www.openssl.org/source/license.html
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//
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// or
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//
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// Copyright (c) 2023, Christoph Müllner <[email protected]>
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// Copyright (c) 2023, Phoebe Chen <[email protected]>
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// Copyright 2024 Google LLC
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The generated code of this file depends on the following RISC-V extensions:
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// - RV64I
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// - RISC-V Vector ('V') with VLEN >= 128
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// - RISC-V Vector SHA-2 Secure Hash extension ('Zvknhb')
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// - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
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#include <linux/cfi_types.h>
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.text
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.option arch, +zvknhb, +zvkb
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#define STATEP a0
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#define DATA a1
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#define NUM_BLOCKS a2
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#define STATEP_C a3
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#define K a4
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#define MASK v0
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#define INDICES v1
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#define W0 v10 // LMUL=2
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#define W1 v12 // LMUL=2
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#define W2 v14 // LMUL=2
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#define W3 v16 // LMUL=2
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#define VTMP v20 // LMUL=2
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#define FEBA v22 // LMUL=2
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#define HGDC v24 // LMUL=2
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#define PREV_FEBA v26 // LMUL=2
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#define PREV_HGDC v28 // LMUL=2
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// Do 4 rounds of SHA-512. w0 contains the current 4 message schedule words.
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//
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// If not all the message schedule words have been computed yet, then this also
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// computes 4 more message schedule words. w1-w3 contain the next 3 groups of 4
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// message schedule words; this macro computes the group after w3 and writes it
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// to w0. This means that the next (w0, w1, w2, w3) is the current (w1, w2, w3,
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// w0), so the caller must cycle through the registers accordingly.
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.macro sha512_4rounds last, w0, w1, w2, w3
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vle64.v VTMP, (K)
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addi K, K, 32
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vadd.vv VTMP, VTMP, \w0
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vsha2cl.vv HGDC, FEBA, VTMP
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vsha2ch.vv FEBA, HGDC, VTMP
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.if !\last
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vmerge.vvm VTMP, \w2, \w1, MASK
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vsha2ms.vv \w0, VTMP, \w3
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.endif
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.endm
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.macro sha512_16rounds last
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sha512_4rounds \last, W0, W1, W2, W3
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sha512_4rounds \last, W1, W2, W3, W0
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sha512_4rounds \last, W2, W3, W0, W1
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sha512_4rounds \last, W3, W0, W1, W2
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.endm
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// void sha512_transform_zvknhb_zvkb(u64 state[8], const u8 *data,
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// int num_blocks);
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SYM_TYPED_FUNC_START(sha512_transform_zvknhb_zvkb)
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// Setup mask for the vmerge to replace the first word (idx==0) in
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// message scheduling. There are 4 words, so an 8-bit mask suffices.
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vsetivli zero, 1, e8, m1, ta, ma
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vmv.v.i MASK, 0x01
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// Load the state. The state is stored as {a,b,c,d,e,f,g,h}, but we
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// need {f,e,b,a},{h,g,d,c}. The dst vtype is e64m2 and the index vtype
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// is e8mf4. We use index-load with the i8 indices {40, 32, 8, 0},
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// loaded using the 32-bit little endian value 0x00082028.
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li t0, 0x00082028
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vsetivli zero, 1, e32, m1, ta, ma
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vmv.v.x INDICES, t0
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addi STATEP_C, STATEP, 16
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vsetivli zero, 4, e64, m2, ta, ma
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vluxei8.v FEBA, (STATEP), INDICES
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vluxei8.v HGDC, (STATEP_C), INDICES
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.Lnext_block:
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la K, K512
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addi NUM_BLOCKS, NUM_BLOCKS, -1
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// Save the previous state, as it's needed later.
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vmv.v.v PREV_FEBA, FEBA
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vmv.v.v PREV_HGDC, HGDC
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// Load the next 1024-bit message block and endian-swap each 64-bit word
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vle64.v W0, (DATA)
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vrev8.v W0, W0
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addi DATA, DATA, 32
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vle64.v W1, (DATA)
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vrev8.v W1, W1
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addi DATA, DATA, 32
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vle64.v W2, (DATA)
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vrev8.v W2, W2
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addi DATA, DATA, 32
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vle64.v W3, (DATA)
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vrev8.v W3, W3
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addi DATA, DATA, 32
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// Do the 80 rounds of SHA-512.
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sha512_16rounds 0
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sha512_16rounds 0
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sha512_16rounds 0
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sha512_16rounds 0
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sha512_16rounds 1
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// Add the previous state.
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vadd.vv FEBA, FEBA, PREV_FEBA
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vadd.vv HGDC, HGDC, PREV_HGDC
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// Repeat if more blocks remain.
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bnez NUM_BLOCKS, .Lnext_block
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// Store the new state and return.
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vsuxei8.v FEBA, (STATEP), INDICES
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vsuxei8.v HGDC, (STATEP_C), INDICES
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ret
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SYM_FUNC_END(sha512_transform_zvknhb_zvkb)
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.section ".rodata"
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.p2align 3
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.type K512, @object
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K512:
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.dword 0x428a2f98d728ae22, 0x7137449123ef65cd
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.dword 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
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.dword 0x3956c25bf348b538, 0x59f111f1b605d019
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.dword 0x923f82a4af194f9b, 0xab1c5ed5da6d8118
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.dword 0xd807aa98a3030242, 0x12835b0145706fbe
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.dword 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
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.dword 0x72be5d74f27b896f, 0x80deb1fe3b1696b1
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.dword 0x9bdc06a725c71235, 0xc19bf174cf692694
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.dword 0xe49b69c19ef14ad2, 0xefbe4786384f25e3
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.dword 0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65
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.dword 0x2de92c6f592b0275, 0x4a7484aa6ea6e483
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.dword 0x5cb0a9dcbd41fbd4, 0x76f988da831153b5
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.dword 0x983e5152ee66dfab, 0xa831c66d2db43210
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.dword 0xb00327c898fb213f, 0xbf597fc7beef0ee4
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.dword 0xc6e00bf33da88fc2, 0xd5a79147930aa725
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.dword 0x06ca6351e003826f, 0x142929670a0e6e70
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.dword 0x27b70a8546d22ffc, 0x2e1b21385c26c926
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.dword 0x4d2c6dfc5ac42aed, 0x53380d139d95b3df
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.dword 0x650a73548baf63de, 0x766a0abb3c77b2a8
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.dword 0x81c2c92e47edaee6, 0x92722c851482353b
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.dword 0xa2bfe8a14cf10364, 0xa81a664bbc423001
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.dword 0xc24b8b70d0f89791, 0xc76c51a30654be30
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.dword 0xd192e819d6ef5218, 0xd69906245565a910
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.dword 0xf40e35855771202a, 0x106aa07032bbd1b8
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.dword 0x19a4c116b8d2d0c8, 0x1e376c085141ab53
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.dword 0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8
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.dword 0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb
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.dword 0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3
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.dword 0x748f82ee5defb2fc, 0x78a5636f43172f60
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.dword 0x84c87814a1f0ab72, 0x8cc702081a6439ec
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.dword 0x90befffa23631e28, 0xa4506cebde82bde9
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.dword 0xbef9a3f7b2c67915, 0xc67178f2e372532b
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.dword 0xca273eceea26619c, 0xd186b8c721c0c207
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.dword 0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178
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.dword 0x06f067aa72176fba, 0x0a637dc5a2c898a6
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.dword 0x113f9804bef90dae, 0x1b710b35131c471b
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.dword 0x28db77f523047d84, 0x32caab7b40c72493
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.dword 0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c
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.dword 0x4cc5d4becb3e42b6, 0x597f299cfc657e2a
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.dword 0x5fcb6fab3ad6faec, 0x6c44198c4a475817
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.size K512, . - K512

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