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Sean Christophersonsuryasaimadhu
Sean Christopherson
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suryasaimadhu
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KVM: VMX: Use VMX_FEATURE_* flags to define VMCS control bits
Define the VMCS execution control flags (consumed by KVM) using their associated VMX_FEATURE_* to provide a strong hint that new VMX features are expected to be added to VMX_FEATURE and considered for reporting via /proc/cpuinfo. No functional change intended. Signed-off-by: Sean Christopherson <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
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  • arch/x86/include/asm

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‎arch/x86/include/asm/vmx.h

Lines changed: 55 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -15,67 +15,70 @@
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#include <linux/bitops.h>
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#include <linux/types.h>
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#include <uapi/asm/vmx.h>
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#include <asm/vmxfeatures.h>
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20+
#define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
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/*
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* Definitions of Primary Processor-Based VM-Execution Controls.
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*/
22-
#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
23-
#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
24-
#define CPU_BASED_HLT_EXITING 0x00000080
25-
#define CPU_BASED_INVLPG_EXITING 0x00000200
26-
#define CPU_BASED_MWAIT_EXITING 0x00000400
27-
#define CPU_BASED_RDPMC_EXITING 0x00000800
28-
#define CPU_BASED_RDTSC_EXITING 0x00001000
29-
#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
30-
#define CPU_BASED_CR3_STORE_EXITING 0x00010000
31-
#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
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#define CPU_BASED_CR8_STORE_EXITING 0x00100000
33-
#define CPU_BASED_TPR_SHADOW 0x00200000
34-
#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
35-
#define CPU_BASED_MOV_DR_EXITING 0x00800000
36-
#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
37-
#define CPU_BASED_USE_IO_BITMAPS 0x02000000
38-
#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
39-
#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
40-
#define CPU_BASED_MONITOR_EXITING 0x20000000
41-
#define CPU_BASED_PAUSE_EXITING 0x40000000
42-
#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
25+
#define CPU_BASED_VIRTUAL_INTR_PENDING VMCS_CONTROL_BIT(VIRTUAL_INTR_PENDING)
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#define CPU_BASED_USE_TSC_OFFSETING VMCS_CONTROL_BIT(TSC_OFFSETTING)
27+
#define CPU_BASED_HLT_EXITING VMCS_CONTROL_BIT(HLT_EXITING)
28+
#define CPU_BASED_INVLPG_EXITING VMCS_CONTROL_BIT(INVLPG_EXITING)
29+
#define CPU_BASED_MWAIT_EXITING VMCS_CONTROL_BIT(MWAIT_EXITING)
30+
#define CPU_BASED_RDPMC_EXITING VMCS_CONTROL_BIT(RDPMC_EXITING)
31+
#define CPU_BASED_RDTSC_EXITING VMCS_CONTROL_BIT(RDTSC_EXITING)
32+
#define CPU_BASED_CR3_LOAD_EXITING VMCS_CONTROL_BIT(CR3_LOAD_EXITING)
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#define CPU_BASED_CR3_STORE_EXITING VMCS_CONTROL_BIT(CR3_STORE_EXITING)
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#define CPU_BASED_CR8_LOAD_EXITING VMCS_CONTROL_BIT(CR8_LOAD_EXITING)
35+
#define CPU_BASED_CR8_STORE_EXITING VMCS_CONTROL_BIT(CR8_STORE_EXITING)
36+
#define CPU_BASED_TPR_SHADOW VMCS_CONTROL_BIT(VIRTUAL_TPR)
37+
#define CPU_BASED_VIRTUAL_NMI_PENDING VMCS_CONTROL_BIT(VIRTUAL_NMI_PENDING)
38+
#define CPU_BASED_MOV_DR_EXITING VMCS_CONTROL_BIT(MOV_DR_EXITING)
39+
#define CPU_BASED_UNCOND_IO_EXITING VMCS_CONTROL_BIT(UNCOND_IO_EXITING)
40+
#define CPU_BASED_USE_IO_BITMAPS VMCS_CONTROL_BIT(USE_IO_BITMAPS)
41+
#define CPU_BASED_MONITOR_TRAP_FLAG VMCS_CONTROL_BIT(MONITOR_TRAP_FLAG)
42+
#define CPU_BASED_USE_MSR_BITMAPS VMCS_CONTROL_BIT(USE_MSR_BITMAPS)
43+
#define CPU_BASED_MONITOR_EXITING VMCS_CONTROL_BIT(MONITOR_EXITING)
44+
#define CPU_BASED_PAUSE_EXITING VMCS_CONTROL_BIT(PAUSE_EXITING)
45+
#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS VMCS_CONTROL_BIT(SEC_CONTROLS)
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#define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
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/*
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* Definitions of Secondary Processor-Based VM-Execution Controls.
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*/
49-
#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
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#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
51-
#define SECONDARY_EXEC_DESC 0x00000004
52-
#define SECONDARY_EXEC_RDTSCP 0x00000008
53-
#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
54-
#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
55-
#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
56-
#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
57-
#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
58-
#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
59-
#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
60-
#define SECONDARY_EXEC_RDRAND_EXITING 0x00000800
61-
#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
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#define SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
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#define SECONDARY_EXEC_SHADOW_VMCS 0x00004000
64-
#define SECONDARY_EXEC_ENCLS_EXITING 0x00008000
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#define SECONDARY_EXEC_RDSEED_EXITING 0x00010000
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#define SECONDARY_EXEC_ENABLE_PML 0x00020000
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#define SECONDARY_EXEC_PT_CONCEAL_VMX 0x00080000
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#define SECONDARY_EXEC_XSAVES 0x00100000
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#define SECONDARY_EXEC_PT_USE_GPA 0x01000000
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#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC 0x00400000
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#define SECONDARY_EXEC_TSC_SCALING 0x02000000
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#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES VMCS_CONTROL_BIT(VIRT_APIC_ACCESSES)
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#define SECONDARY_EXEC_ENABLE_EPT VMCS_CONTROL_BIT(EPT)
54+
#define SECONDARY_EXEC_DESC VMCS_CONTROL_BIT(DESC_EXITING)
55+
#define SECONDARY_EXEC_RDTSCP VMCS_CONTROL_BIT(RDTSCP)
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#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE VMCS_CONTROL_BIT(VIRTUAL_X2APIC)
57+
#define SECONDARY_EXEC_ENABLE_VPID VMCS_CONTROL_BIT(VPID)
58+
#define SECONDARY_EXEC_WBINVD_EXITING VMCS_CONTROL_BIT(WBINVD_EXITING)
59+
#define SECONDARY_EXEC_UNRESTRICTED_GUEST VMCS_CONTROL_BIT(UNRESTRICTED_GUEST)
60+
#define SECONDARY_EXEC_APIC_REGISTER_VIRT VMCS_CONTROL_BIT(APIC_REGISTER_VIRT)
61+
#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY VMCS_CONTROL_BIT(VIRT_INTR_DELIVERY)
62+
#define SECONDARY_EXEC_PAUSE_LOOP_EXITING VMCS_CONTROL_BIT(PAUSE_LOOP_EXITING)
63+
#define SECONDARY_EXEC_RDRAND_EXITING VMCS_CONTROL_BIT(RDRAND_EXITING)
64+
#define SECONDARY_EXEC_ENABLE_INVPCID VMCS_CONTROL_BIT(INVPCID)
65+
#define SECONDARY_EXEC_ENABLE_VMFUNC VMCS_CONTROL_BIT(VMFUNC)
66+
#define SECONDARY_EXEC_SHADOW_VMCS VMCS_CONTROL_BIT(SHADOW_VMCS)
67+
#define SECONDARY_EXEC_ENCLS_EXITING VMCS_CONTROL_BIT(ENCLS_EXITING)
68+
#define SECONDARY_EXEC_RDSEED_EXITING VMCS_CONTROL_BIT(RDSEED_EXITING)
69+
#define SECONDARY_EXEC_ENABLE_PML VMCS_CONTROL_BIT(PAGE_MOD_LOGGING)
70+
#define SECONDARY_EXEC_PT_CONCEAL_VMX VMCS_CONTROL_BIT(PT_CONCEAL_VMX)
71+
#define SECONDARY_EXEC_XSAVES VMCS_CONTROL_BIT(XSAVES)
72+
#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC)
73+
#define SECONDARY_EXEC_PT_USE_GPA VMCS_CONTROL_BIT(PT_USE_GPA)
74+
#define SECONDARY_EXEC_TSC_SCALING VMCS_CONTROL_BIT(TSC_SCALING)
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#define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE 0x04000000
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74-
#define PIN_BASED_EXT_INTR_MASK 0x00000001
75-
#define PIN_BASED_NMI_EXITING 0x00000008
76-
#define PIN_BASED_VIRTUAL_NMIS 0x00000020
77-
#define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
78-
#define PIN_BASED_POSTED_INTR 0x00000080
77+
#define PIN_BASED_EXT_INTR_MASK VMCS_CONTROL_BIT(INTR_EXITING)
78+
#define PIN_BASED_NMI_EXITING VMCS_CONTROL_BIT(NMI_EXITING)
79+
#define PIN_BASED_VIRTUAL_NMIS VMCS_CONTROL_BIT(VIRTUAL_NMIS)
80+
#define PIN_BASED_VMX_PREEMPTION_TIMER VMCS_CONTROL_BIT(PREEMPTION_TIMER)
81+
#define PIN_BASED_POSTED_INTR VMCS_CONTROL_BIT(POSTED_INTR)
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#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
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@@ -114,7 +117,9 @@
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#define VMX_MISC_MSR_LIST_MULTIPLIER 512
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/* VMFUNC functions */
117-
#define VMX_VMFUNC_EPTP_SWITCHING 0x00000001
120+
#define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28)
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122+
#define VMX_VMFUNC_EPTP_SWITCHING VMFUNC_CONTROL_BIT(EPTP_SWITCHING)
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#define VMFUNC_EPTP_ENTRIES 512
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static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)

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