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konradybciobebarino
konradybcio
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clk: qcom: smd: Add support for MSM8992/4 rpm clocks
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992, MSM8994 (and APQ variants) for clients to vote on. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Fixed up binding numbers] Signed-off-by: Stephen Boyd <[email protected]>
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‎Documentation/devicetree/bindings/clock/qcom,rpmcc.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@ Required properties :
1818
"qcom,rpmcc-msm8976", "qcom,rpmcc"
1919
"qcom,rpmcc-apq8064", "qcom,rpmcc"
2020
"qcom,rpmcc-ipq806x", "qcom,rpmcc"
21+
"qcom,rpmcc-msm8992",·"qcom,rpmcc"
22+
"qcom,rpmcc-msm8994",·"qcom,rpmcc"
2123
"qcom,rpmcc-msm8996", "qcom,rpmcc"
2224
"qcom,rpmcc-msm8998", "qcom,rpmcc"
2325
"qcom,rpmcc-qcs404", "qcom,rpmcc"

‎drivers/clk/qcom/clk-smd-rpm.c

Lines changed: 171 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -623,6 +623,175 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
623623
.num_clks = ARRAY_SIZE(msm8976_clks),
624624
};
625625

626+
/* msm8992 */
627+
DEFINE_CLK_SMD_RPM(msm8992, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
628+
DEFINE_CLK_SMD_RPM(msm8992, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
629+
DEFINE_CLK_SMD_RPM(msm8992, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
630+
DEFINE_CLK_SMD_RPM(msm8992, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
631+
DEFINE_CLK_SMD_RPM(msm8992, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
632+
DEFINE_CLK_SMD_RPM(msm8992, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
633+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk1, bb_clk1_a, 1);
634+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk1_pin, bb_clk1_a_pin, 1);
635+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk2, bb_clk2_a, 2);
636+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk2_pin, bb_clk2_a_pin, 2);
637+
638+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk1, div_clk1_a, 11);
639+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk2, div_clk2_a, 12);
640+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13);
641+
DEFINE_CLK_SMD_RPM(msm8992, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
642+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8);
643+
DEFINE_CLK_SMD_RPM(msm8992, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
644+
QCOM_SMD_RPM_BUS_CLK, 3);
645+
DEFINE_CLK_SMD_RPM_QDSS(msm8992, qdss_clk, qdss_a_clk,
646+
QCOM_SMD_RPM_MISC_CLK, 1);
647+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk1, rf_clk1_a, 4);
648+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk2, rf_clk2_a, 5);
649+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk1_pin, rf_clk1_a_pin, 4);
650+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk2_pin, rf_clk2_a_pin, 5);
651+
652+
DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
653+
DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
654+
655+
static struct clk_smd_rpm *msm8992_clks[] = {
656+
[RPM_SMD_PNOC_CLK] = &msm8992_pnoc_clk,
657+
[RPM_SMD_PNOC_A_CLK] = &msm8992_pnoc_a_clk,
658+
[RPM_SMD_OCMEMGX_CLK] = &msm8992_ocmemgx_clk,
659+
[RPM_SMD_OCMEMGX_A_CLK] = &msm8992_ocmemgx_a_clk,
660+
[RPM_SMD_BIMC_CLK] = &msm8992_bimc_clk,
661+
[RPM_SMD_BIMC_A_CLK] = &msm8992_bimc_a_clk,
662+
[RPM_SMD_CNOC_CLK] = &msm8992_cnoc_clk,
663+
[RPM_SMD_CNOC_A_CLK] = &msm8992_cnoc_a_clk,
664+
[RPM_SMD_GFX3D_CLK_SRC] = &msm8992_gfx3d_clk_src,
665+
[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8992_gfx3d_a_clk_src,
666+
[RPM_SMD_SNOC_CLK] = &msm8992_snoc_clk,
667+
[RPM_SMD_SNOC_A_CLK] = &msm8992_snoc_a_clk,
668+
[RPM_SMD_BB_CLK1] = &msm8992_bb_clk1,
669+
[RPM_SMD_BB_CLK1_A] = &msm8992_bb_clk1_a,
670+
[RPM_SMD_BB_CLK1_PIN] = &msm8992_bb_clk1_pin,
671+
[RPM_SMD_BB_CLK1_A_PIN] = &msm8992_bb_clk1_a_pin,
672+
[RPM_SMD_BB_CLK2] = &msm8992_bb_clk2,
673+
[RPM_SMD_BB_CLK2_A] = &msm8992_bb_clk2_a,
674+
[RPM_SMD_BB_CLK2_PIN] = &msm8992_bb_clk2_pin,
675+
[RPM_SMD_BB_CLK2_A_PIN] = &msm8992_bb_clk2_a_pin,
676+
[RPM_SMD_DIV_CLK1] = &msm8992_div_clk1,
677+
[RPM_SMD_DIV_A_CLK1] = &msm8992_div_clk1_a,
678+
[RPM_SMD_DIV_CLK2] = &msm8992_div_clk2,
679+
[RPM_SMD_DIV_A_CLK2] = &msm8992_div_clk2_a,
680+
[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
681+
[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
682+
[RPM_SMD_IPA_CLK] = &msm8992_ipa_clk,
683+
[RPM_SMD_IPA_A_CLK] = &msm8992_ipa_a_clk,
684+
[RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
685+
[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
686+
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8992_mmssnoc_ahb_clk,
687+
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8992_mmssnoc_ahb_a_clk,
688+
[RPM_SMD_QDSS_CLK] = &msm8992_qdss_clk,
689+
[RPM_SMD_QDSS_A_CLK] = &msm8992_qdss_a_clk,
690+
[RPM_SMD_RF_CLK1] = &msm8992_rf_clk1,
691+
[RPM_SMD_RF_CLK1_A] = &msm8992_rf_clk1_a,
692+
[RPM_SMD_RF_CLK2] = &msm8992_rf_clk2,
693+
[RPM_SMD_RF_CLK2_A] = &msm8992_rf_clk2_a,
694+
[RPM_SMD_RF_CLK1_PIN] = &msm8992_rf_clk1_pin,
695+
[RPM_SMD_RF_CLK1_A_PIN] = &msm8992_rf_clk1_a_pin,
696+
[RPM_SMD_RF_CLK2_PIN] = &msm8992_rf_clk2_pin,
697+
[RPM_SMD_RF_CLK2_A_PIN] = &msm8992_rf_clk2_a_pin,
698+
[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
699+
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
700+
[RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
701+
[RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
702+
};
703+
704+
static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
705+
.clks = msm8992_clks,
706+
.num_clks = ARRAY_SIZE(msm8992_clks),
707+
};
708+
709+
/* msm8994 */
710+
DEFINE_CLK_SMD_RPM(msm8994, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
711+
DEFINE_CLK_SMD_RPM(msm8994, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
712+
DEFINE_CLK_SMD_RPM(msm8994, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
713+
DEFINE_CLK_SMD_RPM(msm8994, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
714+
DEFINE_CLK_SMD_RPM(msm8994, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
715+
DEFINE_CLK_SMD_RPM(msm8994, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
716+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk1, bb_clk1_a, 1);
717+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk1_pin, bb_clk1_a_pin, 1);
718+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk2, bb_clk2_a, 2);
719+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk2_pin, bb_clk2_a_pin, 2);
720+
721+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk1, div_clk1_a, 11);
722+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk2, div_clk2_a, 12);
723+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk3, div_clk3_a, 13);
724+
DEFINE_CLK_SMD_RPM(msm8994, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
725+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, ln_bb_clk, ln_bb_a_clk, 8);
726+
DEFINE_CLK_SMD_RPM(msm8994, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
727+
QCOM_SMD_RPM_BUS_CLK, 3);
728+
DEFINE_CLK_SMD_RPM_QDSS(msm8994, qdss_clk, qdss_a_clk,
729+
QCOM_SMD_RPM_MISC_CLK, 1);
730+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk1, rf_clk1_a, 4);
731+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk2, rf_clk2_a, 5);
732+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk1_pin, rf_clk1_a_pin, 4);
733+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk2_pin, rf_clk2_a_pin, 5);
734+
735+
DEFINE_CLK_SMD_RPM(msm8994, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
736+
DEFINE_CLK_SMD_RPM(msm8994, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
737+
DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
738+
739+
static struct clk_smd_rpm *msm8994_clks[] = {
740+
[RPM_SMD_PNOC_CLK] = &msm8994_pnoc_clk,
741+
[RPM_SMD_PNOC_A_CLK] = &msm8994_pnoc_a_clk,
742+
[RPM_SMD_OCMEMGX_CLK] = &msm8994_ocmemgx_clk,
743+
[RPM_SMD_OCMEMGX_A_CLK] = &msm8994_ocmemgx_a_clk,
744+
[RPM_SMD_BIMC_CLK] = &msm8994_bimc_clk,
745+
[RPM_SMD_BIMC_A_CLK] = &msm8994_bimc_a_clk,
746+
[RPM_SMD_CNOC_CLK] = &msm8994_cnoc_clk,
747+
[RPM_SMD_CNOC_A_CLK] = &msm8994_cnoc_a_clk,
748+
[RPM_SMD_GFX3D_CLK_SRC] = &msm8994_gfx3d_clk_src,
749+
[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8994_gfx3d_a_clk_src,
750+
[RPM_SMD_SNOC_CLK] = &msm8994_snoc_clk,
751+
[RPM_SMD_SNOC_A_CLK] = &msm8994_snoc_a_clk,
752+
[RPM_SMD_BB_CLK1] = &msm8994_bb_clk1,
753+
[RPM_SMD_BB_CLK1_A] = &msm8994_bb_clk1_a,
754+
[RPM_SMD_BB_CLK1_PIN] = &msm8994_bb_clk1_pin,
755+
[RPM_SMD_BB_CLK1_A_PIN] = &msm8994_bb_clk1_a_pin,
756+
[RPM_SMD_BB_CLK2] = &msm8994_bb_clk2,
757+
[RPM_SMD_BB_CLK2_A] = &msm8994_bb_clk2_a,
758+
[RPM_SMD_BB_CLK2_PIN] = &msm8994_bb_clk2_pin,
759+
[RPM_SMD_BB_CLK2_A_PIN] = &msm8994_bb_clk2_a_pin,
760+
[RPM_SMD_DIV_CLK1] = &msm8994_div_clk1,
761+
[RPM_SMD_DIV_A_CLK1] = &msm8994_div_clk1_a,
762+
[RPM_SMD_DIV_CLK2] = &msm8994_div_clk2,
763+
[RPM_SMD_DIV_A_CLK2] = &msm8994_div_clk2_a,
764+
[RPM_SMD_DIV_CLK3] = &msm8994_div_clk3,
765+
[RPM_SMD_DIV_A_CLK3] = &msm8994_div_clk3_a,
766+
[RPM_SMD_IPA_CLK] = &msm8994_ipa_clk,
767+
[RPM_SMD_IPA_A_CLK] = &msm8994_ipa_a_clk,
768+
[RPM_SMD_LN_BB_CLK] = &msm8994_ln_bb_clk,
769+
[RPM_SMD_LN_BB_A_CLK] = &msm8994_ln_bb_a_clk,
770+
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8994_mmssnoc_ahb_clk,
771+
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8994_mmssnoc_ahb_a_clk,
772+
[RPM_SMD_QDSS_CLK] = &msm8994_qdss_clk,
773+
[RPM_SMD_QDSS_A_CLK] = &msm8994_qdss_a_clk,
774+
[RPM_SMD_RF_CLK1] = &msm8994_rf_clk1,
775+
[RPM_SMD_RF_CLK1_A] = &msm8994_rf_clk1_a,
776+
[RPM_SMD_RF_CLK2] = &msm8994_rf_clk2,
777+
[RPM_SMD_RF_CLK2_A] = &msm8994_rf_clk2_a,
778+
[RPM_SMD_RF_CLK1_PIN] = &msm8994_rf_clk1_pin,
779+
[RPM_SMD_RF_CLK1_A_PIN] = &msm8994_rf_clk1_a_pin,
780+
[RPM_SMD_RF_CLK2_PIN] = &msm8994_rf_clk2_pin,
781+
[RPM_SMD_RF_CLK2_A_PIN] = &msm8994_rf_clk2_a_pin,
782+
[RPM_SMD_CE1_CLK] = &msm8994_ce1_clk,
783+
[RPM_SMD_CE1_A_CLK] = &msm8994_ce1_a_clk,
784+
[RPM_SMD_CE2_CLK] = &msm8994_ce2_clk,
785+
[RPM_SMD_CE2_A_CLK] = &msm8994_ce2_a_clk,
786+
[RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
787+
[RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
788+
};
789+
790+
static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
791+
.clks = msm8994_clks,
792+
.num_clks = ARRAY_SIZE(msm8994_clks),
793+
};
794+
626795
/* msm8996 */
627796
DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
628797
DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
@@ -895,6 +1064,8 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
8951064
{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
8961065
{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
8971066
{ .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
1067+
{ .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
1068+
{ .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
8981069
{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
8991070
{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
9001071
{ .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },

‎include/dt-bindings/clock/qcom,rpmcc.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -145,5 +145,9 @@
145145
#define RPM_SMD_LN_BB_CLK2_A_PIN 99
146146
#define RPM_SMD_SYSMMNOC_CLK 100
147147
#define RPM_SMD_SYSMMNOC_A_CLK 101
148+
#define RPM_SMD_CE2_CLK 102
149+
#define RPM_SMD_CE2_A_CLK 103
150+
#define RPM_SMD_CE3_CLK 104
151+
#define RPM_SMD_CE3_A_CLK 105
148152

149153
#endif

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