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Marc Zyngieroupton
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KVM: arm64: Rely on visibility to let PIR*_ELx/TCR2_ELx UNDEF
With a visibility defined for these registers, there is no need to check again for S1PIE or TCRX being implemented as perform_access() already handles it. Reviewed-by: Mark Brown <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Oliver Upton <[email protected]>
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arch/arm64/kvm/sys_regs.c

Lines changed: 3 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -369,18 +369,6 @@ static bool access_rw(struct kvm_vcpu *vcpu,
369369
return true;
370370
}
371371

372-
static bool check_s1pie_access_rw(struct kvm_vcpu *vcpu,
373-
struct sys_reg_params *p,
374-
const struct sys_reg_desc *r)
375-
{
376-
if (!kvm_has_s1pie(vcpu->kvm)) {
377-
kvm_inject_undefined(vcpu);
378-
return false;
379-
}
380-
381-
return access_rw(vcpu, p, r);
382-
}
383-
384372
/*
385373
* See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
386374
*/
@@ -445,10 +433,6 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu,
445433
bool was_enabled = vcpu_has_cache_enabled(vcpu);
446434
u64 val, mask, shift;
447435

448-
if (reg_to_encoding(r) == SYS_TCR2_EL1 &&
449-
!kvm_has_tcr2(vcpu->kvm))
450-
return undef_access(vcpu, p, r);
451-
452436
BUG_ON(!p->is_write);
453437

454438
get_access_mask(r, &mask, &shift);
@@ -467,18 +451,6 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu,
467451
return true;
468452
}
469453

470-
static bool access_tcr2_el2(struct kvm_vcpu *vcpu,
471-
struct sys_reg_params *p,
472-
const struct sys_reg_desc *r)
473-
{
474-
if (!kvm_has_tcr2(vcpu->kvm)) {
475-
kvm_inject_undefined(vcpu);
476-
return false;
477-
}
478-
479-
return access_rw(vcpu, p, r);
480-
}
481-
482454
static bool access_actlr(struct kvm_vcpu *vcpu,
483455
struct sys_reg_params *p,
484456
const struct sys_reg_desc *r)
@@ -2937,7 +2909,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
29372909
EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
29382910
EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
29392911
EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2940-
EL2_REG_FILTERED(TCR2_EL2, access_tcr2_el2, reset_val, TCR2_EL2_RES1,
2912+
EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1,
29412913
tcr2_el2_visibility),
29422914
EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
29432915
EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
@@ -2966,9 +2938,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
29662938
EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
29672939

29682940
EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2969-
EL2_REG_FILTERED(PIRE0_EL2, check_s1pie_access_rw, reset_val, 0,
2941+
EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0,
29702942
s1pie_el2_visibility),
2971-
EL2_REG_FILTERED(PIR_EL2, check_s1pie_access_rw, reset_val, 0,
2943+
EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0,
29722944
s1pie_el2_visibility),
29732945
EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
29742946

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