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Evan Quanalexdeucher
Evan Quan
authored and
alexdeucher
committed
drm/amd/powerplay: move dpm feature enablement checking to smu_cmn.c
Considering it is shared by all ASICs and smu_cmn.c should be the right place. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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10 files changed

+95
-87
lines changed

10 files changed

+95
-87
lines changed

‎drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -540,29 +540,6 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
540540
return ret;
541541
}
542542

543-
int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
544-
{
545-
struct smu_feature *feature = &smu->smu_feature;
546-
int feature_id;
547-
int ret = 0;
548-
549-
if (smu->is_apu)
550-
return 1;
551-
feature_id = smu_cmn_to_asic_specific_index(smu,
552-
CMN2ASIC_MAPPING_FEATURE,
553-
mask);
554-
if (feature_id < 0)
555-
return 0;
556-
557-
WARN_ON(feature_id > feature->feature_num);
558-
559-
mutex_lock(&feature->mutex);
560-
ret = test_bit(feature_id, feature->enabled);
561-
mutex_unlock(&feature->mutex);
562-
563-
return ret;
564-
}
565-
566543
int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
567544
bool enable)
568545
{

‎drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
280280

281281
/* socclk dpm table setup */
282282
dpm_table = &dpm_context->dpm_tables.soc_table;
283-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
283+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
284284
ret = smu_v11_0_set_single_dpm_table(smu,
285285
SMU_SOCCLK,
286286
dpm_table);
@@ -298,7 +298,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
298298

299299
/* gfxclk dpm table setup */
300300
dpm_table = &dpm_context->dpm_tables.gfx_table;
301-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
301+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
302302
ret = smu_v11_0_set_single_dpm_table(smu,
303303
SMU_GFXCLK,
304304
dpm_table);
@@ -316,7 +316,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
316316

317317
/* memclk dpm table setup */
318318
dpm_table = &dpm_context->dpm_tables.uclk_table;
319-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
319+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
320320
ret = smu_v11_0_set_single_dpm_table(smu,
321321
SMU_UCLK,
322322
dpm_table);
@@ -334,7 +334,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
334334

335335
/* fclk dpm table setup */
336336
dpm_table = &dpm_context->dpm_tables.fclk_table;
337-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
337+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
338338
ret = smu_v11_0_set_single_dpm_table(smu,
339339
SMU_FCLK,
340340
dpm_table);
@@ -650,31 +650,31 @@ static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
650650
* We can use Average_* for dpm disabled case.
651651
* But this is available for gfxclk/uclk/socclk/vclk/dclk.
652652
*/
653-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
653+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
654654
member_type = METRICS_CURR_GFXCLK;
655655
else
656656
member_type = METRICS_AVERAGE_GFXCLK;
657657
break;
658658
case PPCLK_UCLK:
659-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
659+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
660660
member_type = METRICS_CURR_UCLK;
661661
else
662662
member_type = METRICS_AVERAGE_UCLK;
663663
break;
664664
case PPCLK_SOCCLK:
665-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
665+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
666666
member_type = METRICS_CURR_SOCCLK;
667667
else
668668
member_type = METRICS_AVERAGE_SOCCLK;
669669
break;
670670
case PPCLK_VCLK:
671-
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
671+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
672672
member_type = METRICS_CURR_VCLK;
673673
else
674674
member_type = METRICS_AVERAGE_VCLK;
675675
break;
676676
case PPCLK_DCLK:
677-
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
677+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
678678
member_type = METRICS_CURR_DCLK;
679679
else
680680
member_type = METRICS_AVERAGE_DCLK;
@@ -820,7 +820,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu,
820820
uint32_t freq;
821821
int ret = 0;
822822

823-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
823+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
824824
(feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
825825
freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
826826
ret = smu_send_smc_msg_with_param(smu,
@@ -834,7 +834,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu,
834834
}
835835
}
836836

837-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
837+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
838838
(feature_mask & FEATURE_DPM_UCLK_MASK)) {
839839
freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
840840
ret = smu_send_smc_msg_with_param(smu,
@@ -848,7 +848,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu,
848848
}
849849
}
850850

851-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
851+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
852852
(feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
853853
freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
854854
ret = smu_send_smc_msg_with_param(smu,
@@ -1837,7 +1837,7 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
18371837
int ret = 0;
18381838

18391839
if (enable) {
1840-
if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1840+
if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
18411841
ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
18421842
if (ret) {
18431843
dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
@@ -1846,7 +1846,7 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
18461846
}
18471847
power_gate->vcn_gated = false;
18481848
} else {
1849-
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1849+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
18501850
ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
18511851
if (ret) {
18521852
dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
@@ -2285,6 +2285,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
22852285
.init_display_count = NULL,
22862286
.set_allowed_mask = smu_v11_0_set_allowed_mask,
22872287
.get_enabled_mask = smu_v11_0_get_enabled_mask,
2288+
.feature_is_enabled = smu_cmn_feature_is_enabled,
22882289
.notify_display_change = NULL,
22892290
.set_power_limit = smu_v11_0_set_power_limit,
22902291
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,

‎drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -533,6 +533,7 @@ struct pptable_funcs {
533533
int (*init_display_count)(struct smu_context *smu, uint32_t count);
534534
int (*set_allowed_mask)(struct smu_context *smu);
535535
int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
536+
int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
536537
int (*notify_display_change)(struct smu_context *smu);
537538
int (*set_power_limit)(struct smu_context *smu, uint32_t n);
538539
int (*init_max_sustainable_clocks)(struct smu_context *smu);
@@ -728,8 +729,6 @@ extern const struct amd_ip_funcs smu_ip_funcs;
728729
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
729730
extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
730731

731-
extern int smu_feature_is_enabled(struct smu_context *smu,
732-
enum smu_feature_mask mask);
733732
extern int smu_feature_set_enabled(struct smu_context *smu,
734733
enum smu_feature_mask mask, bool enable);
735734

‎drivers/gpu/drm/amd/powerplay/navi10_ppt.c

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -601,7 +601,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
601601

602602
/* socclk dpm table setup */
603603
dpm_table = &dpm_context->dpm_tables.soc_table;
604-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
604+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
605605
ret = smu_v11_0_set_single_dpm_table(smu,
606606
SMU_SOCCLK,
607607
dpm_table);
@@ -619,7 +619,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
619619

620620
/* gfxclk dpm table setup */
621621
dpm_table = &dpm_context->dpm_tables.gfx_table;
622-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
622+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
623623
ret = smu_v11_0_set_single_dpm_table(smu,
624624
SMU_GFXCLK,
625625
dpm_table);
@@ -637,7 +637,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
637637

638638
/* uclk dpm table setup */
639639
dpm_table = &dpm_context->dpm_tables.uclk_table;
640-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
640+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
641641
ret = smu_v11_0_set_single_dpm_table(smu,
642642
SMU_UCLK,
643643
dpm_table);
@@ -655,7 +655,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
655655

656656
/* vclk dpm table setup */
657657
dpm_table = &dpm_context->dpm_tables.vclk_table;
658-
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
658+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
659659
ret = smu_v11_0_set_single_dpm_table(smu,
660660
SMU_VCLK,
661661
dpm_table);
@@ -673,7 +673,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
673673

674674
/* dclk dpm table setup */
675675
dpm_table = &dpm_context->dpm_tables.dclk_table;
676-
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
676+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
677677
ret = smu_v11_0_set_single_dpm_table(smu,
678678
SMU_DCLK,
679679
dpm_table);
@@ -691,7 +691,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
691691

692692
/* dcefclk dpm table setup */
693693
dpm_table = &dpm_context->dpm_tables.dcef_table;
694-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
694+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
695695
ret = smu_v11_0_set_single_dpm_table(smu,
696696
SMU_DCEFCLK,
697697
dpm_table);
@@ -709,7 +709,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
709709

710710
/* pixelclk dpm table setup */
711711
dpm_table = &dpm_context->dpm_tables.pixel_table;
712-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
712+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
713713
ret = smu_v11_0_set_single_dpm_table(smu,
714714
SMU_PIXCLK,
715715
dpm_table);
@@ -727,7 +727,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
727727

728728
/* displayclk dpm table setup */
729729
dpm_table = &dpm_context->dpm_tables.display_table;
730-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
730+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
731731
ret = smu_v11_0_set_single_dpm_table(smu,
732732
SMU_DISPCLK,
733733
dpm_table);
@@ -745,7 +745,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
745745

746746
/* phyclk dpm table setup */
747747
dpm_table = &dpm_context->dpm_tables.phy_table;
748-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
748+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
749749
ret = smu_v11_0_set_single_dpm_table(smu,
750750
SMU_PHYCLK,
751751
dpm_table);
@@ -772,14 +772,14 @@ static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
772772

773773
if (enable) {
774774
/* vcn dpm on is a prerequisite for vcn power gate messages */
775-
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
775+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
776776
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
777777
if (ret)
778778
return ret;
779779
}
780780
power_gate->vcn_gated = false;
781781
} else {
782-
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
782+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
783783
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
784784
if (ret)
785785
return ret;
@@ -797,14 +797,14 @@ static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
797797
int ret = 0;
798798

799799
if (enable) {
800-
if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
800+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
801801
ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
802802
if (ret)
803803
return ret;
804804
}
805805
power_gate->jpeg_gated = false;
806806
} else {
807-
if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
807+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
808808
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
809809
if (ret)
810810
return ret;
@@ -1249,7 +1249,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
12491249
if (ret)
12501250
return ret;
12511251

1252-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1252+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
12531253
ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
12541254
if (ret)
12551255
return ret;
@@ -1565,7 +1565,7 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
15651565
}
15661566
}
15671567

1568-
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1568+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
15691569
ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
15701570
if (ret) {
15711571
dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
@@ -2300,6 +2300,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
23002300
.init_display_count = smu_v11_0_init_display_count,
23012301
.set_allowed_mask = smu_v11_0_set_allowed_mask,
23022302
.get_enabled_mask = smu_v11_0_get_enabled_mask,
2303+
.feature_is_enabled = smu_cmn_feature_is_enabled,
23032304
.notify_display_change = smu_v11_0_notify_display_change,
23042305
.set_power_limit = smu_v11_0_set_power_limit,
23052306
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,

‎drivers/gpu/drm/amd/powerplay/renoir_ppt.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -463,14 +463,14 @@ static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
463463

464464
if (enable) {
465465
/* vcn dpm on is a prerequisite for vcn power gate messages */
466-
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
466+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
467467
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
468468
if (ret)
469469
return ret;
470470
}
471471
power_gate->vcn_gated = false;
472472
} else {
473-
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
473+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
474474
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
475475
if (ret)
476476
return ret;
@@ -488,14 +488,14 @@ static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
488488
int ret = 0;
489489

490490
if (enable) {
491-
if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
491+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
492492
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
493493
if (ret)
494494
return ret;
495495
}
496496
power_gate->jpeg_gated = false;
497497
} else {
498-
if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
498+
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
499499
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
500500
if (ret)
501501
return ret;
@@ -571,7 +571,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
571571
};
572572

573573
for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
574-
if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
574+
if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
575575
continue;
576576

577577
clk_type = clk_feature_map[i].clk_type;
@@ -1019,6 +1019,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
10191019
.fini_smc_tables = smu_v12_0_fini_smc_tables,
10201020
.set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
10211021
.get_enabled_mask = smu_v12_0_get_enabled_mask,
1022+
.feature_is_enabled = smu_cmn_feature_is_enabled,
10221023
.get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
10231024
.mode2_reset = smu_v12_0_mode2_reset,
10241025
.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,

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