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Merge tag 'v5.7-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers
Refactor the mmsys to reflect that it's a clock driver and the entry point for the DRM subsystem. Replace clk-provider.h include with of_clk.h for mach-mediatek * tag 'v5.7-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: ARM: mediatek: Replace <linux/clk-provider.h> by <linux/of_clk.h> soc: mediatek: Missing platform_device_unregister() on error in mtk_mmsys_probe() soc: mediatek: mmsys: Drop <linux/clk-provider.h> soc / drm: mediatek: Fix mediatek-drm device probing soc / drm: mediatek: Move routing control to mmsys device clk / soc: mediatek: Move mt8173 MMSYS to platform driver dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller drm/mediatek: Omit warning on probe defers Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
Mediatek mmsys controller
22
============================
33

4-
The Mediatek mmsys controller provides various clocks to the system.
4+
The Mediatek mmsys system controller provides clock control, routing control,
5+
and miscellaneous control in mmsys partition.
56

67
Required Properties:
78

@@ -15,13 +16,13 @@ Required Properties:
1516
- "mediatek,mt8183-mmsys", "syscon"
1617
- #clock-cells: Must be 1
1718

18-
The mmsys controller uses the common clk binding from
19+
For the clock control, the mmsys controller uses the common clk binding from
1920
Documentation/devicetree/bindings/clock/clock-bindings.txt
2021
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
2122

2223
Example:
2324

24-
mmsys: clock-controller@14000000 {
25+
mmsys: syscon@14000000 {
2526
compatible = "mediatek,mt8173-mmsys", "syscon";
2627
reg = <0 0x14000000 0 0x1000>;
2728
#clock-cells = <1>;

‎arch/arm/mach-mediatek/mediatek.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
#include <linux/io.h>
1010
#include <asm/mach/arch.h>
1111
#include <linux/of.h>
12-
#include <linux/clk-provider.h>
12+
#include <linux/of_clk.h>
1313
#include <linux/clocksource.h>
1414

1515

‎drivers/clk/mediatek/Kconfig

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -274,6 +274,13 @@ config COMMON_CLK_MT8173
274274
---help---
275275
This driver supports MediaTek MT8173 clocks.
276276

277+
config COMMON_CLK_MT8173_MMSYS
278+
bool "Clock driver for MediaTek MT8173 mmsys"
279+
depends on COMMON_CLK_MT8173
280+
default COMMON_CLK_MT8173
281+
help
282+
This driver supports MediaTek MT8173 mmsys clocks.
283+
277284
config COMMON_CLK_MT8183
278285
bool "Clock driver for MediaTek MT8183"
279286
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

‎drivers/clk/mediatek/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
4141
obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
4242
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
4343
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
44+
obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
4445
obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
4546
obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o
4647
obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o

‎drivers/clk/mediatek/clk-mt8173-mm.c

Lines changed: 146 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,146 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/*
3+
* Copyright (c) 2014 MediaTek Inc.
4+
* Author: James Liao <[email protected]>
5+
*/
6+
7+
#include <linux/clk-provider.h>
8+
#include <linux/of_device.h>
9+
#include <linux/platform_device.h>
10+
11+
#include "clk-gate.h"
12+
#include "clk-mtk.h"
13+
14+
#include <dt-bindings/clock/mt8173-clk.h>
15+
16+
static const struct mtk_gate_regs mm0_cg_regs = {
17+
.set_ofs = 0x0104,
18+
.clr_ofs = 0x0108,
19+
.sta_ofs = 0x0100,
20+
};
21+
22+
static const struct mtk_gate_regs mm1_cg_regs = {
23+
.set_ofs = 0x0114,
24+
.clr_ofs = 0x0118,
25+
.sta_ofs = 0x0110,
26+
};
27+
28+
#define GATE_MM0(_id, _name, _parent, _shift) { \
29+
.id = _id, \
30+
.name = _name, \
31+
.parent_name = _parent, \
32+
.regs = &mm0_cg_regs, \
33+
.shift = _shift, \
34+
.ops = &mtk_clk_gate_ops_setclr, \
35+
}
36+
37+
#define GATE_MM1(_id, _name, _parent, _shift) { \
38+
.id = _id, \
39+
.name = _name, \
40+
.parent_name = _parent, \
41+
.regs = &mm1_cg_regs, \
42+
.shift = _shift, \
43+
.ops = &mtk_clk_gate_ops_setclr, \
44+
}
45+
46+
static const struct mtk_gate mt8173_mm_clks[] = {
47+
/* MM0 */
48+
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
49+
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
50+
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
51+
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
52+
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
53+
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
54+
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
55+
GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
56+
GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
57+
GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
58+
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
59+
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
60+
GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
61+
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
62+
GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
63+
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
64+
GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
65+
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
66+
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
67+
GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
68+
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
69+
GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
70+
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
71+
GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
72+
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
73+
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
74+
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
75+
GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
76+
GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
77+
GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
78+
GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
79+
/* MM1 */
80+
GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
81+
GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
82+
GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
83+
GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
84+
GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
85+
GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
86+
GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
87+
GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
88+
GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
89+
GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
90+
GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
91+
GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
92+
GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
93+
GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
94+
GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
95+
GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
96+
GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
97+
GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
98+
GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
99+
GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
100+
GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
101+
};
102+
103+
struct clk_mt8173_mm_driver_data {
104+
const struct mtk_gate *gates_clk;
105+
int gates_num;
106+
};
107+
108+
static const struct clk_mt8173_mm_driver_data mt8173_mmsys_driver_data = {
109+
.gates_clk = mt8173_mm_clks,
110+
.gates_num = ARRAY_SIZE(mt8173_mm_clks),
111+
};
112+
113+
static int clk_mt8173_mm_probe(struct platform_device *pdev)
114+
{
115+
struct device *dev = &pdev->dev;
116+
struct device_node *node = dev->parent->of_node;
117+
const struct clk_mt8173_mm_driver_data *data;
118+
struct clk_onecell_data *clk_data;
119+
int ret;
120+
121+
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
122+
if (!clk_data)
123+
return -ENOMEM;
124+
125+
data = &mt8173_mmsys_driver_data;
126+
127+
ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num,
128+
clk_data);
129+
if (ret)
130+
return ret;
131+
132+
ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
133+
if (ret)
134+
return ret;
135+
136+
return 0;
137+
}
138+
139+
static struct platform_driver clk_mt8173_mm_drv = {
140+
.driver = {
141+
.name = "clk-mt8173-mm",
142+
},
143+
.probe = clk_mt8173_mm_probe,
144+
};
145+
146+
builtin_platform_driver(clk_mt8173_mm_drv);

‎drivers/clk/mediatek/clk-mt8173.c

Lines changed: 0 additions & 104 deletions
Original file line numberDiff line numberDiff line change
@@ -753,93 +753,6 @@ static const struct mtk_gate img_clks[] __initconst = {
753753
GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
754754
};
755755

756-
static const struct mtk_gate_regs mm0_cg_regs __initconst = {
757-
.set_ofs = 0x0104,
758-
.clr_ofs = 0x0108,
759-
.sta_ofs = 0x0100,
760-
};
761-
762-
static const struct mtk_gate_regs mm1_cg_regs __initconst = {
763-
.set_ofs = 0x0114,
764-
.clr_ofs = 0x0118,
765-
.sta_ofs = 0x0110,
766-
};
767-
768-
#define GATE_MM0(_id, _name, _parent, _shift) { \
769-
.id = _id, \
770-
.name = _name, \
771-
.parent_name = _parent, \
772-
.regs = &mm0_cg_regs, \
773-
.shift = _shift, \
774-
.ops = &mtk_clk_gate_ops_setclr, \
775-
}
776-
777-
#define GATE_MM1(_id, _name, _parent, _shift) { \
778-
.id = _id, \
779-
.name = _name, \
780-
.parent_name = _parent, \
781-
.regs = &mm1_cg_regs, \
782-
.shift = _shift, \
783-
.ops = &mtk_clk_gate_ops_setclr, \
784-
}
785-
786-
static const struct mtk_gate mm_clks[] __initconst = {
787-
/* MM0 */
788-
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
789-
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
790-
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
791-
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
792-
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
793-
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
794-
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
795-
GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
796-
GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
797-
GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
798-
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
799-
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
800-
GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
801-
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
802-
GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
803-
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
804-
GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
805-
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
806-
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
807-
GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
808-
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
809-
GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
810-
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
811-
GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
812-
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
813-
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
814-
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
815-
GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
816-
GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
817-
GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
818-
GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
819-
/* MM1 */
820-
GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
821-
GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
822-
GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
823-
GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
824-
GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
825-
GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
826-
GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
827-
GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
828-
GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
829-
GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
830-
GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
831-
GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
832-
GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
833-
GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
834-
GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
835-
GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
836-
GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
837-
GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
838-
GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
839-
GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
840-
GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
841-
};
842-
843756
static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
844757
.set_ofs = 0x0000,
845758
.clr_ofs = 0x0004,
@@ -1144,23 +1057,6 @@ static void __init mtk_imgsys_init(struct device_node *node)
11441057
}
11451058
CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
11461059

1147-
static void __init mtk_mmsys_init(struct device_node *node)
1148-
{
1149-
struct clk_onecell_data *clk_data;
1150-
int r;
1151-
1152-
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
1153-
1154-
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
1155-
clk_data);
1156-
1157-
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1158-
if (r)
1159-
pr_err("%s(): could not register clock provider: %d\n",
1160-
__func__, r);
1161-
}
1162-
CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt8173-mmsys", mtk_mmsys_init);
1163-
11641060
static void __init mtk_vdecsys_init(struct device_node *node)
11651061
{
11661062
struct clk_onecell_data *clk_data;

‎drivers/gpu/drm/mediatek/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ config DRM_MEDIATEK
1111
select DRM_MIPI_DSI
1212
select DRM_PANEL
1313
select MEMORY
14+
select MTK_MMSYS
1415
select MTK_SMI
1516
select VIDEOMODE_HELPERS
1617
help

‎drivers/gpu/drm/mediatek/mtk_disp_color.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,10 @@ static int mtk_disp_color_probe(struct platform_device *pdev)
119119
ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
120120
&mtk_disp_color_funcs);
121121
if (ret) {
122-
dev_err(dev, "Failed to initialize component: %d\n", ret);
122+
if (ret != -EPROBE_DEFER)
123+
dev_err(dev, "Failed to initialize component: %d\n",
124+
ret);
125+
123126
return ret;
124127
}
125128

‎drivers/gpu/drm/mediatek/mtk_disp_ovl.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -386,7 +386,10 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
386386
ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
387387
&mtk_disp_ovl_funcs);
388388
if (ret) {
389-
dev_err(dev, "Failed to initialize component: %d\n", ret);
389+
if (ret != -EPROBE_DEFER)
390+
dev_err(dev, "Failed to initialize component: %d\n",
391+
ret);
392+
390393
return ret;
391394
}
392395

‎drivers/gpu/drm/mediatek/mtk_disp_rdma.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -294,7 +294,10 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev)
294294
ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
295295
&mtk_disp_rdma_funcs);
296296
if (ret) {
297-
dev_err(dev, "Failed to initialize component: %d\n", ret);
297+
if (ret != -EPROBE_DEFER)
298+
dev_err(dev, "Failed to initialize component: %d\n",
299+
ret);
300+
298301
return ret;
299302
}
300303

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