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Merge tag 'qcom-arm64-for-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
More Qualcomm Arm64 DeviceTree updates for v6.16 Support for CPU frequency scaling is enabled on the X Elite platform. Also on X Elite, support for the HP EliteBook Ultra G1q is introduced. Support for the QCS6490 RB3gen2 Industrial Mezzanine is also added. PCIe controllers and PHYs are described and enabled across IPQ5018, IPQ5332, and IPQ5424. On IPQ9474 the missing MHI register range is added. The TCSR block is described and used to enable download mode flags on IPQ5018. The venus video encoder/decoder is enabled on the MSM8998-based Lenovo Miix 630 laptop. The crypto engine is enabled on QCM2290 and QCS615. Bluetooth is enabled on the QCM2210-based RB1 board. The Fairphone FP5 gains Displayport sound support. SAR2130P display nodes are added. On 8cx Gen3 the sensor remoteproc (SLPI) is introduced and this is enabled on Lenovo Thinkpad X13s and the CRD. The SDM845-based Samsung Galaxy S9 gains graphics, modem and initial sound support. On SDX75 the QPIC BAM and NAND support is added, and these are enabled on the IDP board. LLCC is added for SM8750. SM8550 gains Iris video decoder support. For X Elite, Lenovo ThinkPad T14s support for the SDX62 modem, as well as audio headset, is added. ASUS Vivobook S 15 gains Bluetooth support, Microsoft Surface Laptop 7 models gets support for DP over USB Type-C, HP Omnibook X 14 gains audio support. The devkit gets the USB multiport controller and the two USB Type-A ports described. Additionally a variety of Devicetree fixes are introduced, primarily identified through binding validation. * tag 'qcom-arm64-for-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (58 commits) arm64: dts: qcom: sm4450: Add RPMh power domains support arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: add retimers, dp altmode support arm64: dts: qcom: ipq5424: Enable PCIe PHYs and controllers arm64: dts: qcom: ipq5424: Add PCIe PHYs and controller nodes arm64: dts: qcom: sc7280: Mark FastRPC context banks as dma-coherent arm64: dts: qcom: sdx75-idp: Enable QPIC BAM & QPIC NAND support arm64: dts: qcom: sdx75: Add QPIC NAND support arm64: dts: qcom: sdx75: Add QPIC BAM support arm64: dts: qcom: qcm2290: Add crypto engine arm64: dts: qcom: x1e80100-vivobook-s15: Add bluetooth arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties arm64: dts: qcom: qcs615: Fix up UFS clocks arm64: dts: qcom: sa8775p: Clean up the PSCI PDs arm64: dts: qcom: msm8996-oneplus: Add SLPI VDD_PX arm64: dts: qcom: sm6350-pdx213: Wire up USB regulators arm64: dts: qcom: msm8998-yoshino: Add QUSB2PHY VDD supply arm64: dts: qcom: msm8998-mtp: Add QUSB2PHY VDD supply arm64: dts: qcom: msm8998-fxtec: Add QUSB2PHY VDD supply arm64: dts: qcom: qcs615: Remove disallowed property from AOSS_QMP node arm64: dts: qcom: msm8998: Remove mdss_hdmi_phy phandle argument ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 13649a4 + 654ac80 commit b5125e6

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‎Documentation/devicetree/bindings/arm/qcom.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1141,6 +1141,7 @@ properties:
11411141
- asus,vivobook-s15
11421142
- asus,zenbook-a14-ux3407ra
11431143
- dell,xps13-9345
1144+
- hp,elitebook-ultra-g1q
11441145
- hp,omnibook-x14
11451146
- lenovo,yoga-slim7x
11461147
- microsoft,romulus13

‎arch/arm64/boot/dts/qcom/Makefile

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,9 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb
118118
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
119119

120120
qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo
121+
qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo
121122

123+
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb
122124
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb
123125
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb
124126
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
@@ -311,6 +313,8 @@ x1e80100-crd-el2-dtbs := x1e80100-crd.dtb x1-el2.dtbo
311313
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb x1e80100-crd-el2.dtb
312314
x1e80100-dell-xps13-9345-el2-dtbs := x1e80100-dell-xps13-9345.dtb x1-el2.dtbo
313315
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb x1e80100-dell-xps13-9345-el2.dtb
316+
x1e80100-hp-elitebook-ultra-g1q-el2-dtbs := x1e80100-hp-elitebook-ultra-g1q.dtb x1-el2.dtbo
317+
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-elitebook-ultra-g1q.dtb x1e80100-hp-elitebook-ultra-g1q-el2.dtb
314318
x1e80100-hp-omnibook-x14-el2-dtbs := x1e80100-hp-omnibook-x14.dtb x1-el2.dtbo
315319
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omnibook-x14-el2.dtb
316320
x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.dtbo

‎arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@
99

1010
#include "ipq5018.dtsi"
1111

12+
#include <dt-bindings/gpio/gpio.h>
13+
1214
/ {
1315
model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";
1416
compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";
@@ -28,6 +30,20 @@
2830
status = "okay";
2931
};
3032

33+
&pcie0 {
34+
pinctrl-0 = <&pcie0_default>;
35+
pinctrl-names = "default";
36+
37+
perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
38+
wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
39+
40+
status = "okay";
41+
};
42+
43+
&pcie0_phy {
44+
status = "okay";
45+
};
46+
3147
&sdhc_1 {
3248
pinctrl-0 = <&sdc_default_state>;
3349
pinctrl-names = "default";
@@ -43,6 +59,30 @@
4359
};
4460

4561
&tlmm {
62+
pcie0_default: pcie0-default-state {
63+
clkreq-n-pins {
64+
pins = "gpio14";
65+
function = "pcie0_clk";
66+
drive-strength = <8>;
67+
bias-pull-up;
68+
};
69+
70+
perst-n-pins {
71+
pins = "gpio15";
72+
function = "gpio";
73+
drive-strength = <8>;
74+
bias-pull-up;
75+
output-low;
76+
};
77+
78+
wake-n-pins {
79+
pins = "gpio16";
80+
function = "pcie0_wake";
81+
drive-strength = <8>;
82+
bias-pull-up;
83+
};
84+
};
85+
4686
sdc_default_state: sdc-default-state {
4787
clk-pins {
4888
pins = "gpio9";

‎arch/arm64/boot/dts/qcom/ipq5018.dtsi

Lines changed: 244 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,7 @@
7979
firmware {
8080
scm {
8181
compatible = "qcom,scm-ipq5018", "qcom,scm";
82+
qcom,dload-mode = <&tcsr 0x6100>;
8283
qcom,sdi-enabled;
8384
};
8485
};
@@ -147,6 +148,40 @@
147148
status = "disabled";
148149
};
149150

151+
pcie1_phy: phy@7e000 {
152+
compatible = "qcom,ipq5018-uniphy-pcie-phy";
153+
reg = <0x0007e000 0x800>;
154+
155+
clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
156+
157+
resets = <&gcc GCC_PCIE1_PHY_BCR>,
158+
<&gcc GCC_PCIE1PHY_PHY_BCR>;
159+
160+
#clock-cells = <0>;
161+
#phy-cells = <0>;
162+
163+
num-lanes = <1>;
164+
165+
status = "disabled";
166+
};
167+
168+
pcie0_phy: phy@86000 {
169+
compatible = "qcom,ipq5018-uniphy-pcie-phy";
170+
reg = <0x00086000 0x1000>;
171+
172+
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
173+
174+
resets = <&gcc GCC_PCIE0_PHY_BCR>,
175+
<&gcc GCC_PCIE0PHY_PHY_BCR>;
176+
177+
#clock-cells = <0>;
178+
#phy-cells = <0>;
179+
180+
num-lanes = <2>;
181+
182+
status = "disabled";
183+
};
184+
150185
tlmm: pinctrl@1000000 {
151186
compatible = "qcom,ipq5018-tlmm";
152187
reg = <0x01000000 0x300000>;
@@ -170,8 +205,8 @@
170205
reg = <0x01800000 0x80000>;
171206
clocks = <&xo_board_clk>,
172207
<&sleep_clk>,
173-
<0>,
174-
<0>,
208+
<&pcie0_phy>,
209+
<&pcie1_phy>,
175210
<0>,
176211
<0>,
177212
<0>,
@@ -187,6 +222,11 @@
187222
#hwlock-cells = <1>;
188223
};
189224

225+
tcsr: syscon@1937000 {
226+
compatible = "qcom,tcsr-ipq5018", "syscon";
227+
reg = <0x01937000 0x21000>;
228+
};
229+
190230
sdhc_1: mmc@7804000 {
191231
compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
192232
reg = <0x7804000 0x1000>;
@@ -387,6 +427,208 @@
387427
status = "disabled";
388428
};
389429
};
430+
431+
pcie1: pcie@80000000 {
432+
compatible = "qcom,pcie-ipq5018";
433+
reg = <0x80000000 0xf1d>,
434+
<0x80000f20 0xa8>,
435+
<0x80001000 0x1000>,
436+
<0x00078000 0x3000>,
437+
<0x80100000 0x1000>,
438+
<0x0007b000 0x1000>;
439+
reg-names = "dbi",
440+
"elbi",
441+
"atu",
442+
"parf",
443+
"config",
444+
"mhi";
445+
device_type = "pci";
446+
linux,pci-domain = <1>;
447+
bus-range = <0x00 0xff>;
448+
num-lanes = <1>;
449+
#address-cells = <3>;
450+
#size-cells = <2>;
451+
452+
/* The controller supports Gen3, but the connected PHY is Gen2-capable */
453+
max-link-speed = <2>;
454+
455+
phys = <&pcie1_phy>;
456+
phy-names ="pciephy";
457+
458+
ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>,
459+
<0x02000000 0 0x80300000 0x80300000 0 0x10000000>;
460+
461+
msi-map = <0x0 &v2m0 0x0 0xff8>;
462+
463+
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
464+
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
465+
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
466+
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
467+
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
468+
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
469+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
470+
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
471+
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
472+
interrupt-names = "msi0",
473+
"msi1",
474+
"msi2",
475+
"msi3",
476+
"msi4",
477+
"msi5",
478+
"msi6",
479+
"msi7",
480+
"global";
481+
482+
#interrupt-cells = <1>;
483+
interrupt-map-mask = <0 0 0 0x7>;
484+
interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>,
485+
<0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>,
486+
<0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>,
487+
<0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>;
488+
489+
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
490+
<&gcc GCC_PCIE1_AXI_M_CLK>,
491+
<&gcc GCC_PCIE1_AXI_S_CLK>,
492+
<&gcc GCC_PCIE1_AHB_CLK>,
493+
<&gcc GCC_PCIE1_AUX_CLK>,
494+
<&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>;
495+
clock-names = "iface",
496+
"axi_m",
497+
"axi_s",
498+
"ahb",
499+
"aux",
500+
"axi_bridge";
501+
502+
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
503+
<&gcc GCC_PCIE1_SLEEP_ARES>,
504+
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
505+
<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
506+
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
507+
<&gcc GCC_PCIE1_AHB_ARES>,
508+
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>,
509+
<&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>;
510+
reset-names = "pipe",
511+
"sleep",
512+
"sticky",
513+
"axi_m",
514+
"axi_s",
515+
"ahb",
516+
"axi_m_sticky",
517+
"axi_s_sticky";
518+
519+
status = "disabled";
520+
521+
pcie@0 {
522+
device_type = "pci";
523+
reg = <0x0 0x0 0x0 0x0 0x0>;
524+
bus-range = <0x01 0xff>;
525+
526+
#address-cells = <3>;
527+
#size-cells = <2>;
528+
ranges;
529+
};
530+
};
531+
532+
pcie0: pcie@a0000000 {
533+
compatible = "qcom,pcie-ipq5018";
534+
reg = <0xa0000000 0xf1d>,
535+
<0xa0000f20 0xa8>,
536+
<0xa0001000 0x1000>,
537+
<0x00080000 0x3000>,
538+
<0xa0100000 0x1000>,
539+
<0x00083000 0x1000>;
540+
reg-names = "dbi",
541+
"elbi",
542+
"atu",
543+
"parf",
544+
"config",
545+
"mhi";
546+
device_type = "pci";
547+
linux,pci-domain = <0>;
548+
bus-range = <0x00 0xff>;
549+
num-lanes = <2>;
550+
#address-cells = <3>;
551+
#size-cells = <2>;
552+
553+
/* The controller supports Gen3, but the connected PHY is Gen2-capable */
554+
max-link-speed = <2>;
555+
556+
phys = <&pcie0_phy>;
557+
phy-names ="pciephy";
558+
559+
ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
560+
<0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
561+
562+
msi-map = <0x0 &v2m0 0x0 0xff8>;
563+
564+
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
565+
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
566+
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
567+
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
568+
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
569+
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
570+
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
571+
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
572+
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
573+
interrupt-names = "msi0",
574+
"msi1",
575+
"msi2",
576+
"msi3",
577+
"msi4",
578+
"msi5",
579+
"msi6",
580+
"msi7",
581+
"global";
582+
583+
#interrupt-cells = <1>;
584+
interrupt-map-mask = <0 0 0 0x7>;
585+
interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
586+
<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
587+
<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
588+
<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
589+
590+
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
591+
<&gcc GCC_PCIE0_AXI_M_CLK>,
592+
<&gcc GCC_PCIE0_AXI_S_CLK>,
593+
<&gcc GCC_PCIE0_AHB_CLK>,
594+
<&gcc GCC_PCIE0_AUX_CLK>,
595+
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
596+
clock-names = "iface",
597+
"axi_m",
598+
"axi_s",
599+
"ahb",
600+
"aux",
601+
"axi_bridge";
602+
603+
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
604+
<&gcc GCC_PCIE0_SLEEP_ARES>,
605+
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
606+
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
607+
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
608+
<&gcc GCC_PCIE0_AHB_ARES>,
609+
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
610+
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
611+
reset-names = "pipe",
612+
"sleep",
613+
"sticky",
614+
"axi_m",
615+
"axi_s",
616+
"ahb",
617+
"axi_m_sticky",
618+
"axi_s_sticky";
619+
620+
status = "disabled";
621+
622+
pcie@0 {
623+
device_type = "pci";
624+
reg = <0x0 0x0 0x0 0x0 0x0>;
625+
bus-range = <0x01 0xff>;
626+
627+
#address-cells = <3>;
628+
#size-cells = <2>;
629+
ranges;
630+
};
631+
};
390632
};
391633

392634
timer {

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