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airliedairlied
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nouveau/gsp: move to 535.113.01
This moves the initial effort to the latest 535 firmware. The gsp msg structs have changed, and the message passing also. The wpr also seems to have some struct changes. This version of the firmware will be what we are stuck on for a while, until we can refactor the driver and work out a better path forward. Reviewed-by: Danilo Krummrich <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/alloc/alloc_channel.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/alloc/alloc_channel.h

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#ifndef __src_common_sdk_nvidia_inc_alloc_alloc_channel_h__
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#define __src_common_sdk_nvidia_inc_alloc_alloc_channel_h__
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#include <nvrm/535.54.03/common/sdk/nvidia/inc/nvlimits.h>
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#include <nvrm/535.113.01/common/sdk/nvidia/inc/nvlimits.h>
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
@@ -116,6 +116,9 @@ typedef struct NV_MEMORY_DESC_PARAMS {
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#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000
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#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001
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#define CC_CHAN_ALLOC_IV_SIZE_DWORD 3U
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#define CC_CHAN_ALLOC_NONCE_SIZE_DWORD 8U
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typedef struct NV_CHANNEL_ALLOC_PARAMS {
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NvHandle hObjectError; // error context DMA
@@ -154,6 +157,12 @@ typedef struct NV_CHANNEL_ALLOC_PARAMS {
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NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved
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NvU32 ProcessID; // reserved
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NvU32 SubProcessID; // reserved
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// IV used for CPU-side encryption / GPU-side decryption.
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NvU32 encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved
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// IV used for CPU-side decryption / GPU-side encryption.
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NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved
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// Nonce used CPU-side signing / GPU-side signature verification.
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NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved
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} NV_CHANNEL_ALLOC_PARAMS;
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typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS;

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl0000.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl0000.h

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#ifndef __src_common_sdk_nvidia_inc_class_cl0000_h__
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#define __src_common_sdk_nvidia_inc_class_cl0000_h__
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#include <nvrm/535.54.03/common/sdk/nvidia/inc/nvlimits.h>
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#include <nvrm/535.113.01/common/sdk/nvidia/inc/nvlimits.h>
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl0005.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl0005.h

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#ifndef __src_common_sdk_nvidia_inc_class_cl0005_h__
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#define __src_common_sdk_nvidia_inc_class_cl0005_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl0080.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl0080.h

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#ifndef __src_common_sdk_nvidia_inc_class_cl0080_h__
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#define __src_common_sdk_nvidia_inc_class_cl0080_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl2080.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl2080.h

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#ifndef __src_common_sdk_nvidia_inc_class_cl2080_h__
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#define __src_common_sdk_nvidia_inc_class_cl2080_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl2080_notification.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl2080_notification.h

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#ifndef __src_common_sdk_nvidia_inc_class_cl2080_notification_h__
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#define __src_common_sdk_nvidia_inc_class_cl2080_notification_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl84a0.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl84a0.h

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#ifndef __src_common_sdk_nvidia_inc_class_cl84a0_h__
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#define __src_common_sdk_nvidia_inc_class_cl84a0_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl90f1.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl90f1.h

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#ifndef __src_common_sdk_nvidia_inc_class_cl90f1_h__
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#define __src_common_sdk_nvidia_inc_class_cl90f1_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/clc0b5sw.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/clc0b5sw.h

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#ifndef __src_common_sdk_nvidia_inc_class_clc0b5sw_h__
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#define __src_common_sdk_nvidia_inc_class_clc0b5sw_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h renamed to ‎drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h

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#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073common_h__
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#define __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073common_h__
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
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/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

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