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yiliu1765joergroedel
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iommu/vt-d: Rename cap_5lp_support to cap_fl5lp_support
This renaming better describes it is for first level page table (a.k.a first stage page table since VT-d spec 3.4). Signed-off-by: Yi Liu <[email protected]> Reviewed-by: Kevin Tian <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lu Baolu <[email protected]> Signed-off-by: Joerg Roedel <[email protected]>
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+6
-6
lines changed

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+6
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lines changed

drivers/iommu/intel/cap_audit.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ static inline void check_dmar_capabilities(struct intel_iommu *a,
3737
MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_MHMV_MASK);
3838
MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_IRO_MASK);
3939

40-
CHECK_FEATURE_MISMATCH(a, b, cap, 5lp_support, CAP_FL5LP_MASK);
40+
CHECK_FEATURE_MISMATCH(a, b, cap, fl5lp_support, CAP_FL5LP_MASK);
4141
CHECK_FEATURE_MISMATCH(a, b, cap, fl1gp_support, CAP_FL1GP_MASK);
4242
CHECK_FEATURE_MISMATCH(a, b, cap, read_drain, CAP_RD_MASK);
4343
CHECK_FEATURE_MISMATCH(a, b, cap, write_drain, CAP_WD_MASK);
@@ -84,7 +84,7 @@ static int cap_audit_hotplug(struct intel_iommu *iommu, enum cap_audit_type type
8484
goto out;
8585
}
8686

87-
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, 5lp_support, CAP_FL5LP_MASK);
87+
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl5lp_support, CAP_FL5LP_MASK);
8888
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl1gp_support, CAP_FL1GP_MASK);
8989
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, read_drain, CAP_RD_MASK);
9090
CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, write_drain, CAP_WD_MASK);

drivers/iommu/intel/iommu.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -404,7 +404,7 @@ static unsigned long __iommu_calculate_sagaw(struct intel_iommu *iommu)
404404
{
405405
unsigned long fl_sagaw, sl_sagaw;
406406

407-
fl_sagaw = BIT(2) | (cap_5lp_support(iommu->cap) ? BIT(3) : 0);
407+
fl_sagaw = BIT(2) | (cap_fl5lp_support(iommu->cap) ? BIT(3) : 0);
408408
sl_sagaw = cap_sagaw(iommu->cap);
409409

410410
/* Second level only. */

drivers/iommu/intel/iommu.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,7 @@
146146
/*
147147
* Decoding Capability Register
148148
*/
149-
#define cap_5lp_support(c) (((c) >> 60) & 1)
149+
#define cap_fl5lp_support(c) (((c) >> 60) & 1)
150150
#define cap_pi_support(c) (((c) >> 59) & 1)
151151
#define cap_fl1gp_support(c) (((c) >> 56) & 1)
152152
#define cap_read_drain(c) (((c) >> 55) & 1)

drivers/iommu/intel/pasid.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -519,7 +519,7 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
519519
}
520520
}
521521

522-
if ((flags & PASID_FLAG_FL5LP) && !cap_5lp_support(iommu->cap)) {
522+
if ((flags & PASID_FLAG_FL5LP) && !cap_fl5lp_support(iommu->cap)) {
523523
pr_err("No 5-level paging support for first-level on %s\n",
524524
iommu->name);
525525
return -EINVAL;

drivers/iommu/intel/svm.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,7 @@ void intel_svm_check(struct intel_iommu *iommu)
164164
}
165165

166166
if (cpu_feature_enabled(X86_FEATURE_LA57) &&
167-
!cap_5lp_support(iommu->cap)) {
167+
!cap_fl5lp_support(iommu->cap)) {
168168
pr_err("%s SVM disabled, incompatible paging mode\n",
169169
iommu->name);
170170
return;

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