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21 | 21 | /* Register offsets */
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22 | 22 | #define REG_GEN3_IRQSTR 0x04
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23 | 23 | #define REG_GEN3_IRQMSK 0x08
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24 |
| -#define REG_GEN3_IRQCTL 0x0C |
| 24 | +#define REG_GEN3_IRQCTL 0x0c |
25 | 25 | #define REG_GEN3_IRQEN 0x10
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26 | 26 | #define REG_GEN3_IRQTEMP1 0x14
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27 | 27 | #define REG_GEN3_IRQTEMP2 0x18
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28 |
| -#define REG_GEN3_IRQTEMP3 0x1C |
| 28 | +#define REG_GEN3_IRQTEMP3 0x1c |
29 | 29 | #define REG_GEN3_THCTR 0x20
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30 | 30 | #define REG_GEN3_TEMP 0x28
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31 | 31 | #define REG_GEN3_THCODE1 0x50
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38 | 38 | #define REG_GEN4_THSFMON00 0x180
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39 | 39 | #define REG_GEN4_THSFMON01 0x184
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40 | 40 | #define REG_GEN4_THSFMON02 0x188
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41 |
| -#define REG_GEN4_THSFMON15 0x1BC |
42 |
| -#define REG_GEN4_THSFMON16 0x1C0 |
43 |
| -#define REG_GEN4_THSFMON17 0x1C4 |
| 41 | +#define REG_GEN4_THSFMON15 0x1bc |
| 42 | +#define REG_GEN4_THSFMON16 0x1c0 |
| 43 | +#define REG_GEN4_THSFMON17 0x1c4 |
44 | 44 |
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45 | 45 | /* IRQ{STR,MSK,EN} bits */
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46 | 46 | #define IRQ_TEMP1 BIT(0)
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57 | 57 | /* THSCP bits */
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58 | 58 | #define THSCP_COR_PARA_VLD (BIT(15) | BIT(14))
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59 | 59 |
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60 |
| -#define CTEMP_MASK 0xFFF |
| 60 | +#define CTEMP_MASK 0xfff |
61 | 61 |
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62 | 62 | #define MCELSIUS(temp) ((temp) * 1000)
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63 |
| -#define GEN3_FUSE_MASK 0xFFF |
64 |
| -#define GEN4_FUSE_MASK 0xFFF |
| 63 | +#define GEN3_FUSE_MASK 0xfff |
| 64 | +#define GEN4_FUSE_MASK 0xfff |
65 | 65 |
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66 | 66 | #define TSC_MAX_NUM 5
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67 | 67 |
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