Merge branch 'pci/controller/brcmstb'

- Add missing of_node refcount release after of_parse_phandle() (Stanimir
  Varbanov)

- Add BCM2712 MSI-X DT binding and interrupt controller drivers (Stanimir
  Varbanov)

- Add brcmstb softdep on irq_bcm2712_mip MIP MSI-X interrupt controller
  driver to ensure that it is loaded first (Stanimir Varbanov)

- Add struct brcm_pcie pointer to pcie_cfg_data so we can reference the
  pcie_cfg_data directly instead of copying it to brcm_pcie (Stanimir
  Varbanov)

- Expand inbound window map to 64GB so it can accommodate BCM2712 (Stanimir
  Varbanov)

- Add BCM2712 support and DT updates (Stanimir Varbanov)

- Apply link speed restriction before bringing link up, not after (Jim
  Quinlan)

- Update Max Link Speed in Link Capabilities via the internal writable
  register, not the read-only config register (Jim Quinlan)

- Handle regulator_bulk_get() error to avoid panic when we call
  regulator_bulk_free() later (Jim Quinlan)

- Disable regulators only when removing the bus immediately below a Root
  Port because we don't support regulators deeper in the hierarchy (Jim
  Quinlan)

- Consistently use config access index/data register offsets from the
  SoC-specific pcie_offsets[] table (Jim Quinlan)

- Update MDIO register fields that reduced CMD from 12 bits to 1 and
  widened PORT from 4 bits to 5 and split it into two parts (Jim Quinlan)

- Make const read-only arrays static (Colin Ian King)

* pci/controller/brcmstb:
  PCI: brcmstb: Make const read-only arrays static
  PCI: brcmstb: Make irq_domain_set_info() parameter cast explicit
  PCI: brcmstb: Make two changes in MDIO register fields
  PCI: brcmstb: Use same constant table for config space access
  PCI: brcmstb: Fix potential premature regulator disabling
  PCI: brcmstb: Fix error path after a call to regulator_bulk_get()
  PCI: brcmstb: Do not assume that register field starts at LSB
  PCI: brcmstb: Use internal register to change link capability
  PCI: brcmstb: Set generation limit before PCIe link up
  PCI: brcmstb: Add BCM2712 support
  PCI: brcmstb: Expand inbound window size up to 64GB
  PCI: brcmstb: Reuse pcie_cfg_data structure
  PCI: brcmstb: Add a softdep to MIP MSI-X driver
  irqchip: Add Broadcom BCM2712 MSI-X interrupt controller
  dt-bindings: PCI: brcmstb: Update bindings for PCIe on BCM2712
  dt-bindings: interrupt-controller: Add BCM2712 MSI-X bindings
  PCI: brcmstb: Fix missing of_node_put() in brcm_pcie_probe()

Author: bjorn-helgaas

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
+
+maintainers:
+  - Stanimir Varbanov <[email protected]>
+
+description:
+  This interrupt controller is used to provide interrupt vectors to the
+  generic interrupt controller (GIC) on bcm2712. It will be used as
+  external MSI-X controller for PCIe root complex.
+
+allOf:
+  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
+
+properties:
+  compatible:
+    const: brcm,bcm2712-mip
+
+  reg:
+    items:
+      - description: Base register address
+      - description: PCIe message address
+
+  "#msi-cells":
+    const: 0
+
+  brcm,msi-offset:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Shift the allocated MSI's.
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - msi-controller
+  - msi-ranges
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    axi {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        msi-controller@1000130000 {
+            compatible = "brcm,bcm2712-mip";
+            reg = <0x10 0x00130000 0x00 0xc0>,
+                  <0xff 0xfffff000 0x00 0x1000>;
+            msi-controller;
+            #msi-cells = <0>;
+            msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
+        };
+    };

Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml

@@ -14,6 +14,7 @@ properties:
     items:
       - enum:
           - brcm,bcm2711-pcie # The Raspberry Pi 4
+          - brcm,bcm2712-pcie # Raspberry Pi 5
           - brcm,bcm4908-pcie
           - brcm,bcm7211-pcie # Broadcom STB version of RPi4
           - brcm,bcm7216-pcie # Broadcom 7216 Arm
@@ -101,7 +102,10 @@ properties:
 
   reset-names:
     minItems: 1
-    maxItems: 3
+    items:
+      - enum: [perst, rescal]
+      - const: bridge
+      - const: swinit
 
 required:
   - compatible

drivers/irqchip/Kconfig

@@ -109,6 +109,22 @@ config I8259
 	bool
 	select IRQ_DOMAIN
 
+config BCM2712_MIP
+	tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
+	depends on ARCH_BRCMSTB || COMPILE_TEST
+	default m if ARCH_BRCMSTB
+	depends on ARM_GIC
+	select GENERIC_IRQ_CHIP
+	select IRQ_DOMAIN_HIERARCHY
+	select GENERIC_MSI_IRQ
+	select IRQ_MSI_LIB
+	help
+	  Enable support for the Broadcom BCM2712 MSI-X target peripheral
+	  (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
+	  Raspberry Pi 5.
+
+	  If unsure say n.
+
 config BCM6345_L1_IRQ
 	bool
 	select GENERIC_IRQ_CHIP

drivers/irqchip/Makefile

@@ -63,6 +63,7 @@ obj-$(CONFIG_XTENSA_MX)			+= irq-xtensa-mx.o
 obj-$(CONFIG_XILINX_INTC)		+= irq-xilinx-intc.o
 obj-$(CONFIG_IRQ_CROSSBAR)		+= irq-crossbar.o
 obj-$(CONFIG_SOC_VF610)			+= irq-vf610-mscm-ir.o
+obj-$(CONFIG_BCM2712_MIP)               += irq-bcm2712-mip.o
 obj-$(CONFIG_BCM6345_L1_IRQ)		+= irq-bcm6345-l1.o
 obj-$(CONFIG_BCM7038_L1_IRQ)		+= irq-bcm7038-l1.o
 obj-$(CONFIG_BCM7120_L2_IRQ)		+= irq-bcm7120-l2.o