@@ -583,20 +583,17 @@ Power Management Quality of Service for CPUs
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The power management quality of service (PM QoS) framework in the Linux kernel
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allows kernel code and user space processes to set constraints on various
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energy-efficiency features of the kernel to prevent performance from dropping
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- below a required level. The PM QoS constraints can be set globally, in
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- predefined categories referred to as PM QoS classes, or against individual
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- devices.
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+ below a required level.
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CPU idle time management can be affected by PM QoS in two ways, through the
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- global constraint in the ``PM_QOS_CPU_DMA_LATENCY `` class and through the
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- resume latency constraints for individual CPUs. Kernel code (e.g. device
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- drivers) can set both of them with the help of special internal interfaces
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- provided by the PM QoS framework. User space can modify the former by opening
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- the :file: `cpu_dma_latency ` special device file under :file: `/dev/ ` and writing
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- a binary value (interpreted as a signed 32-bit integer) to it. In turn, the
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- resume latency constraint for a CPU can be modified by user space by writing a
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- string (representing a signed 32-bit integer) to the
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- :file: `power/pm_qos_resume_latency_us ` file under
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+ global CPU latency limit and through the resume latency constraints for
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+ individual CPUs. Kernel code (e.g. device drivers) can set both of them with
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+ the help of special internal interfaces provided by the PM QoS framework. User
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+ space can modify the former by opening the :file: `cpu_dma_latency ` special
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+ device file under :file: `/dev/ ` and writing a binary value (interpreted as a
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+ signed 32-bit integer) to it. In turn, the resume latency constraint for a CPU
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+ can be modified from user space by writing a string (representing a signed
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+ 32-bit integer) to the :file: `power/pm_qos_resume_latency_us ` file under
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:file: `/sys/devices/system/cpu/cpu<N>/ ` in ``sysfs ``, where the CPU number
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``<N> `` is allocated at the system initialization time. Negative values
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will be rejected in both cases and, also in both cases, the written integer
@@ -605,32 +602,34 @@ number will be interpreted as a requested PM QoS constraint in microseconds.
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The requested value is not automatically applied as a new constraint, however,
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as it may be less restrictive (greater in this particular case) than another
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constraint previously requested by someone else. For this reason, the PM QoS
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- framework maintains a list of requests that have been made so far in each
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- global class and for each device, aggregates them and applies the effective
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- (minimum in this particular case) value as the new constraint.
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+ framework maintains a list of requests that have been made so far for the
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+ global CPU latency limit and for each individual CPU, aggregates them and
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+ applies the effective (minimum in this particular case) value as the new
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+ constraint.
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In fact, opening the :file: `cpu_dma_latency ` special device file causes a new
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- PM QoS request to be created and added to the priority list of requests in the
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- ``PM_QOS_CPU_DMA_LATENCY `` class and the file descriptor coming from the
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- "open" operation represents that request. If that file descriptor is then
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- used for writing, the number written to it will be associated with the PM QoS
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- request represented by it as a new requested constraint value. Next, the
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- priority list mechanism will be used to determine the new effective value of
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- the entire list of requests and that effective value will be set as a new
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- constraint. Thus setting a new requested constraint value will only change the
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- real constraint if the effective "list" value is affected by it. In particular,
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- for the ``PM_QOS_CPU_DMA_LATENCY `` class it only affects the real constraint if
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- it is the minimum of the requested constraints in the list. The process holding
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- a file descriptor obtained by opening the :file: `cpu_dma_latency ` special device
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- file controls the PM QoS request associated with that file descriptor, but it
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- controls this particular PM QoS request only.
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+ PM QoS request to be created and added to a global priority list of CPU latency
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+ limit requests and the file descriptor coming from the "open" operation
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+ represents that request. If that file descriptor is then used for writing, the
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+ number written to it will be associated with the PM QoS request represented by
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+ it as a new requested limit value. Next, the priority list mechanism will be
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+ used to determine the new effective value of the entire list of requests and
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+ that effective value will be set as a new CPU latency limit. Thus requesting a
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+ new limit value will only change the real limit if the effective "list" value is
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+ affected by it, which is the case if it is the minimum of the requested values
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+ in the list.
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+
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+ The process holding a file descriptor obtained by opening the
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+ :file: `cpu_dma_latency ` special device file controls the PM QoS request
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+ associated with that file descriptor, but it controls this particular PM QoS
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+ request only.
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Closing the :file: `cpu_dma_latency ` special device file or, more precisely, the
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file descriptor obtained while opening it, causes the PM QoS request associated
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- with that file descriptor to be removed from the `` PM_QOS_CPU_DMA_LATENCY ``
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- class priority list and destroyed. If that happens, the priority list mechanism
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- will be used, again, to determine the new effective value for the whole list
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- and that value will become the new real constraint .
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+ with that file descriptor to be removed from the global priority list of CPU
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+ latency limit requests and destroyed. If that happens, the priority list
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+ mechanism will be used again, to determine the new effective value for the whole
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+ list and that value will become the new limit .
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In turn, for each CPU there is one resume latency PM QoS request associated with
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the :file: `power/pm_qos_resume_latency_us ` file under
@@ -647,10 +646,10 @@ CPU in question every time the list of requests is updated this way or another
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(there may be other requests coming from kernel code in that list).
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CPU idle time governors are expected to regard the minimum of the global
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- effective `` PM_QOS_CPU_DMA_LATENCY `` class constraint and the effective
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- resume latency constraint for the given CPU as the upper limit for the exit
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- latency of the idle states they can select for that CPU. They should never
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- select any idle states with exit latency beyond that limit.
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+ ( effective) CPU latency limit and the effective resume latency constraint for
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+ the given CPU as the upper limit for the exit latency of the idle states that
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+ they are allowed to select for that CPU. They should never select any idle
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+ states with exit latency beyond that limit.
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Idle States Control Via Kernel Command Line
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