Skip to content

Commit bada038

Browse files
bebarinobebarino
committed
Merge tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add SPI Multi I/O Bus and SDHI clocks and resets on RZ/G2L - Add SPI Multi I/O Bus (RPC) clocks on R-Car V3U - Add MediaLB clocks on R-Car H3, M3-W/W+, and M3-N * tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a779[56]x: Add MLP clocks clk: renesas: r9a07g044: Add SDHI clock and reset entries clk: renesas: rzg2l: Add SDHI clk mux support clk: renesas: r8a779a0: Add RPC support clk: renesas: cpg-lib: Move RPC clock registration to the library clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller
2 parents e974872 + 2bd9fee commit bada038

File tree

10 files changed

+318
-87
lines changed

10 files changed

+318
-87
lines changed

‎drivers/clk/renesas/r8a7795-cpg-mssr.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -229,6 +229,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
229229
DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
230230
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
231231
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
232+
DEF_MOD("mlp", 802, R8A7795_CLK_S2D1),
232233
DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
233234
DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
234235
DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),

‎drivers/clk/renesas/r8a7796-cpg-mssr.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
207207
DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
208208
DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
209209
DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
210+
DEF_MOD("mlp", 802, R8A7796_CLK_S2D1),
210211
DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
211212
DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
212213
DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),

‎drivers/clk/renesas/r8a77965-cpg-mssr.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
205205
DEF_MOD("lvds", 727, R8A77965_CLK_S2D1),
206206
DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI),
207207

208+
DEF_MOD("mlp", 802, R8A77965_CLK_S2D1),
208209
DEF_MOD("vin7", 804, R8A77965_CLK_S0D2),
209210
DEF_MOD("vin6", 805, R8A77965_CLK_S0D2),
210211
DEF_MOD("vin5", 806, R8A77965_CLK_S0D2),

‎drivers/clk/renesas/r8a779a0-cpg-mssr.c

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,9 @@ enum rcar_r8a779a0_clk_types {
3737
CLK_TYPE_R8A779A0_SD,
3838
CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
3939
CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
40+
CLK_TYPE_R8A779A0_RPCSRC,
41+
CLK_TYPE_R8A779A0_RPC,
42+
CLK_TYPE_R8A779A0_RPCD2,
4043
};
4144

4245
struct rcar_r8a779a0_cpg_pll_config {
@@ -125,6 +128,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
125128
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
126129
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
127130
DEF_RATE(".oco", CLK_OCO, 32768),
131+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_R8A779A0_RPCSRC, CLK_PLL5),
132+
DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_R8A779A0_RPC, CLK_RPCSRC),
133+
DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_R8A779A0_RPCD2,
134+
R8A779A0_CLK_RPC),
128135

129136
/* Core Clock Outputs */
130137
DEF_Z("z0", R8A779A0_CLK_Z0, CLK_PLL20, 2, 0),
@@ -200,6 +207,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
200207
DEF_MOD("msi3", 621, R8A779A0_CLK_MSO),
201208
DEF_MOD("msi4", 622, R8A779A0_CLK_MSO),
202209
DEF_MOD("msi5", 623, R8A779A0_CLK_MSO),
210+
DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2),
203211
DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
204212
DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
205213
DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
@@ -414,6 +422,15 @@ static struct clk * __init cpg_z_clk_register(const char *name,
414422
return clk;
415423
}
416424

425+
/*
426+
* RPC Clocks
427+
*/
428+
#define CPG_RPCCKCR 0x874
429+
430+
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
431+
{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
432+
};
433+
417434
static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
418435
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
419436
struct clk **clks, void __iomem *base,
@@ -481,6 +498,21 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
481498
div = cpg_pll_config->osc_prediv * core->div;
482499
break;
483500

501+
case CLK_TYPE_R8A779A0_RPCSRC:
502+
return clk_register_divider_table(NULL, core->name,
503+
__clk_get_name(parent), 0,
504+
base + CPG_RPCCKCR, 3, 2, 0,
505+
cpg_rpcsrc_div_table,
506+
&cpg_lock);
507+
508+
case CLK_TYPE_R8A779A0_RPC:
509+
return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
510+
__clk_get_name(parent), notifiers);
511+
512+
case CLK_TYPE_R8A779A0_RPCD2:
513+
return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
514+
__clk_get_name(parent));
515+
484516
default:
485517
return ERR_PTR(-EINVAL);
486518
}

‎drivers/clk/renesas/r9a07g044-cpg.c

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,17 +29,27 @@ enum clk_ids {
2929
CLK_PLL2_DIV16,
3030
CLK_PLL2_DIV20,
3131
CLK_PLL3,
32+
CLK_PLL3_400,
33+
CLK_PLL3_533,
3234
CLK_PLL3_DIV2,
3335
CLK_PLL3_DIV2_4,
3436
CLK_PLL3_DIV2_4_2,
3537
CLK_PLL3_DIV4,
38+
CLK_SEL_PLL3_3,
39+
CLK_DIV_PLL3_C,
3640
CLK_PLL4,
3741
CLK_PLL5,
3842
CLK_PLL5_FOUT3,
3943
CLK_PLL5_250,
4044
CLK_PLL6,
4145
CLK_PLL6_250,
4246
CLK_P1_DIV2,
47+
CLK_PLL2_800,
48+
CLK_PLL2_SDHI_533,
49+
CLK_PLL2_SDHI_400,
50+
CLK_PLL2_SDHI_266,
51+
CLK_SD0_DIV4,
52+
CLK_SD1_DIV4,
4353

4454
/* Module Clocks */
4555
MOD_CLK_BASE,
@@ -56,7 +66,9 @@ static const struct clk_div_table dtable_1_32[] = {
5666
};
5767

5868
/* Mux clock tables */
69+
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
5970
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
71+
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
6072

6173
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
6274
/* External Clock Inputs */
@@ -68,20 +80,31 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
6880
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
6981
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
7082
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
83+
DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
84+
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
7185

7286
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
7387
DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
7488

7589
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
7690

7791
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
92+
DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
93+
DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
94+
DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
95+
DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
96+
7897
DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
7998
DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
8099

81100
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
82101
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
83102
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
84103
DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
104+
DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
105+
sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
106+
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
107+
DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
85108

86109
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
87110
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
@@ -101,6 +124,14 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
101124
DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
102125
DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
103126
sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
127+
DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
128+
DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
129+
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
130+
sel_shdi, ARRAY_SIZE(sel_shdi)),
131+
DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1,
132+
sel_shdi, ARRAY_SIZE(sel_shdi)),
133+
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
134+
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
104135
};
105136

106137
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
@@ -114,6 +145,26 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
114145
0x52c, 0),
115146
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
116147
0x52c, 1),
148+
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
149+
0x550, 0),
150+
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
151+
0x550, 1),
152+
DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
153+
0x554, 0),
154+
DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
155+
0x554, 1),
156+
DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
157+
0x554, 2),
158+
DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
159+
0x554, 3),
160+
DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
161+
0x554, 4),
162+
DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
163+
0x554, 5),
164+
DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
165+
0x554, 6),
166+
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
167+
0x554, 7),
117168
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
118169
0x570, 0),
119170
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -182,6 +233,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
182233
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
183234
DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
184235
DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
236+
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
237+
DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
238+
DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
185239
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
186240
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
187241
DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),

‎drivers/clk/renesas/rcar-cpg-lib.c

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -267,4 +267,87 @@ struct clk * __init cpg_sd_clk_register(const char *name,
267267
return clk;
268268
}
269269

270+
struct rpc_clock {
271+
struct clk_divider div;
272+
struct clk_gate gate;
273+
/*
274+
* One notifier covers both RPC and RPCD2 clocks as they are both
275+
* controlled by the same RPCCKCR register...
276+
*/
277+
struct cpg_simple_notifier csn;
278+
};
279+
280+
static const struct clk_div_table cpg_rpc_div_table[] = {
281+
{ 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
282+
};
283+
284+
struct clk * __init cpg_rpc_clk_register(const char *name,
285+
void __iomem *rpcckcr, const char *parent_name,
286+
struct raw_notifier_head *notifiers)
287+
{
288+
struct rpc_clock *rpc;
289+
struct clk *clk;
290+
291+
rpc = kzalloc(sizeof(*rpc), GFP_KERNEL);
292+
if (!rpc)
293+
return ERR_PTR(-ENOMEM);
294+
295+
rpc->div.reg = rpcckcr;
296+
rpc->div.width = 3;
297+
rpc->div.table = cpg_rpc_div_table;
298+
rpc->div.lock = &cpg_lock;
299+
300+
rpc->gate.reg = rpcckcr;
301+
rpc->gate.bit_idx = 8;
302+
rpc->gate.flags = CLK_GATE_SET_TO_DISABLE;
303+
rpc->gate.lock = &cpg_lock;
304+
305+
rpc->csn.reg = rpcckcr;
306+
307+
clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
308+
&rpc->div.hw, &clk_divider_ops,
309+
&rpc->gate.hw, &clk_gate_ops,
310+
CLK_SET_RATE_PARENT);
311+
if (IS_ERR(clk)) {
312+
kfree(rpc);
313+
return clk;
314+
}
315+
316+
cpg_simple_notifier_register(notifiers, &rpc->csn);
317+
return clk;
318+
}
319+
320+
struct rpcd2_clock {
321+
struct clk_fixed_factor fixed;
322+
struct clk_gate gate;
323+
};
324+
325+
struct clk * __init cpg_rpcd2_clk_register(const char *name,
326+
void __iomem *rpcckcr,
327+
const char *parent_name)
328+
{
329+
struct rpcd2_clock *rpcd2;
330+
struct clk *clk;
331+
332+
rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL);
333+
if (!rpcd2)
334+
return ERR_PTR(-ENOMEM);
335+
336+
rpcd2->fixed.mult = 1;
337+
rpcd2->fixed.div = 2;
338+
339+
rpcd2->gate.reg = rpcckcr;
340+
rpcd2->gate.bit_idx = 9;
341+
rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE;
342+
rpcd2->gate.lock = &cpg_lock;
343+
344+
clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
345+
&rpcd2->fixed.hw, &clk_fixed_factor_ops,
346+
&rpcd2->gate.hw, &clk_gate_ops,
347+
CLK_SET_RATE_PARENT);
348+
if (IS_ERR(clk))
349+
kfree(rpcd2);
350+
351+
return clk;
352+
}
270353

‎drivers/clk/renesas/rcar-cpg-lib.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,4 +30,11 @@ struct clk * __init cpg_sd_clk_register(const char *name,
3030
void __iomem *base, unsigned int offset, const char *parent_name,
3131
struct raw_notifier_head *notifiers, bool skip_first);
3232

33+
struct clk * __init cpg_rpc_clk_register(const char *name,
34+
void __iomem *rpcckcr, const char *parent_name,
35+
struct raw_notifier_head *notifiers);
36+
37+
struct clk * __init cpg_rpcd2_clk_register(const char *name,
38+
void __iomem *rpcckcr,
39+
const char *parent_name);
3340
#endif

0 commit comments

Comments
 (0)