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Merge branch '20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com' into clk-for-6.13
Merge SA8775P multimedia clock bindings through topic branch to allow the constants to be made available to DeviceTree source as well.
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‎Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Camera Clock & Reset Controller on SA8775P
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maintainers:
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- Taniya Das <[email protected]>
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description: |
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Qualcomm camera clock control module provides the clocks, resets and power
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domains on SA8775p.
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See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
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properties:
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compatible:
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enum:
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- qcom,sa8775p-camcc
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clocks:
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items:
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- description: Camera AHB clock from GCC
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- description: Board XO source
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- description: Board active XO source
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- description: Sleep clock source
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power-domains:
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maxItems: 1
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description: MMCX power domain
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required:
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- compatible
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- clocks
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- power-domains
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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clock-controller@ade0000 {
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compatible = "qcom,sa8775p-camcc";
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reg = <0x0ade0000 0x20000>;
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clocks = <&gcc GCC_CAMERA_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>;
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power-domains = <&rpmhpd SA8775P_MMCX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on SA8775P
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maintainers:
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- Taniya Das <[email protected]>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SA8775P.
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See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
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properties:
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compatible:
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enum:
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- qcom,sa8775p-dispcc0
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- qcom,sa8775p-dispcc1
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clocks:
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items:
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- description: GCC AHB clock source
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- description: Board XO source
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- description: Board XO_AO source
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- description: Sleep clock source
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- description: Link clock from DP0 PHY
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- description: VCO DIV clock from DP0 PHY
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- description: Link clock from DP1 PHY
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- description: VCO DIV clock from DP1 PHY
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- description: Byte clock from DSI0 PHY
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- description: Pixel clock from DSI0 PHY
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- description: Byte clock from DSI1 PHY
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- description: Pixel clock from DSI1 PHY
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power-domains:
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maxItems: 1
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description: MMCX power domain
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required:
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- compatible
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- clocks
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- power-domains
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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clock-controller@af00000 {
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compatible = "qcom,sa8775p-dispcc0";
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reg = <0x0af00000 0x20000>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>,
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<&dp_phy0 0>,
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<&dp_phy0 1>,
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<&dp_phy1 2>,
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<&dp_phy1 3>,
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<&dsi_phy0 0>,
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<&dsi_phy0 1>,
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<&dsi_phy1 2>,
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<&dsi_phy1 3>;
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power-domains = <&rpmhpd SA8775P_MMCX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Video Clock & Reset Controller on SA8775P
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maintainers:
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- Taniya Das <[email protected]>
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description: |
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Qualcomm video clock control module provides the clocks, resets and power
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domains on SA8775P.
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See also: include/dt-bindings/clock/qcom,sa8775p-videocc.h
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properties:
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compatible:
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enum:
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- qcom,sa8775p-videocc
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clocks:
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items:
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- description: Video AHB clock from GCC
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- description: Board XO source
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- description: Board active XO source
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- description: Sleep Clock source
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power-domains:
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maxItems: 1
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description: MMCX power domain
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required:
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- compatible
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- clocks
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- power-domains
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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videocc: clock-controller@abf0000 {
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compatible = "qcom,sa8775p-videocc";
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reg = <0x0abf0000 0x10000>;
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clocks = <&gcc GCC_VIDEO_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>;
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power-domains = <&rpmhpd SA8775P_MMCX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎include/dt-bindings/clock/qcom,sa8775p-camcc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H
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#define _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H
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/* CAM_CC clocks */
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#define CAM_CC_CAMNOC_AXI_CLK 0
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#define CAM_CC_CAMNOC_AXI_CLK_SRC 1
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#define CAM_CC_CAMNOC_DCD_XO_CLK 2
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#define CAM_CC_CAMNOC_XO_CLK 3
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#define CAM_CC_CCI_0_CLK 4
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#define CAM_CC_CCI_0_CLK_SRC 5
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#define CAM_CC_CCI_1_CLK 6
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#define CAM_CC_CCI_1_CLK_SRC 7
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#define CAM_CC_CCI_2_CLK 8
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#define CAM_CC_CCI_2_CLK_SRC 9
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#define CAM_CC_CCI_3_CLK 10
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#define CAM_CC_CCI_3_CLK_SRC 11
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#define CAM_CC_CORE_AHB_CLK 12
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#define CAM_CC_CPAS_AHB_CLK 13
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#define CAM_CC_CPAS_FAST_AHB_CLK 14
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#define CAM_CC_CPAS_IFE_0_CLK 15
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#define CAM_CC_CPAS_IFE_1_CLK 16
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#define CAM_CC_CPAS_IFE_LITE_CLK 17
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#define CAM_CC_CPAS_IPE_CLK 18
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#define CAM_CC_CPAS_SFE_LITE_0_CLK 19
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#define CAM_CC_CPAS_SFE_LITE_1_CLK 20
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#define CAM_CC_CPHY_RX_CLK_SRC 21
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#define CAM_CC_CSI0PHYTIMER_CLK 22
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#define CAM_CC_CSI0PHYTIMER_CLK_SRC 23
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#define CAM_CC_CSI1PHYTIMER_CLK 24
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#define CAM_CC_CSI1PHYTIMER_CLK_SRC 25
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#define CAM_CC_CSI2PHYTIMER_CLK 26
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#define CAM_CC_CSI2PHYTIMER_CLK_SRC 27
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#define CAM_CC_CSI3PHYTIMER_CLK 28
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#define CAM_CC_CSI3PHYTIMER_CLK_SRC 29
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#define CAM_CC_CSID_CLK 30
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#define CAM_CC_CSID_CLK_SRC 31
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#define CAM_CC_CSID_CSIPHY_RX_CLK 32
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#define CAM_CC_CSIPHY0_CLK 33
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#define CAM_CC_CSIPHY1_CLK 34
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#define CAM_CC_CSIPHY2_CLK 35
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#define CAM_CC_CSIPHY3_CLK 36
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#define CAM_CC_FAST_AHB_CLK_SRC 37
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#define CAM_CC_GDSC_CLK 38
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#define CAM_CC_ICP_AHB_CLK 39
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#define CAM_CC_ICP_CLK 40
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#define CAM_CC_ICP_CLK_SRC 41
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#define CAM_CC_IFE_0_CLK 42
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#define CAM_CC_IFE_0_CLK_SRC 43
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#define CAM_CC_IFE_0_FAST_AHB_CLK 44
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#define CAM_CC_IFE_1_CLK 45
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#define CAM_CC_IFE_1_CLK_SRC 46
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#define CAM_CC_IFE_1_FAST_AHB_CLK 47
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#define CAM_CC_IFE_LITE_AHB_CLK 48
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#define CAM_CC_IFE_LITE_CLK 49
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#define CAM_CC_IFE_LITE_CLK_SRC 50
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#define CAM_CC_IFE_LITE_CPHY_RX_CLK 51
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#define CAM_CC_IFE_LITE_CSID_CLK 52
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#define CAM_CC_IFE_LITE_CSID_CLK_SRC 53
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#define CAM_CC_IPE_AHB_CLK 54
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#define CAM_CC_IPE_CLK 55
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#define CAM_CC_IPE_CLK_SRC 56
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#define CAM_CC_IPE_FAST_AHB_CLK 57
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#define CAM_CC_MCLK0_CLK 58
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#define CAM_CC_MCLK0_CLK_SRC 59
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#define CAM_CC_MCLK1_CLK 60
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#define CAM_CC_MCLK1_CLK_SRC 61
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#define CAM_CC_MCLK2_CLK 62
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#define CAM_CC_MCLK2_CLK_SRC 63
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#define CAM_CC_MCLK3_CLK 64
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#define CAM_CC_MCLK3_CLK_SRC 65
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#define CAM_CC_PLL0 66
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#define CAM_CC_PLL0_OUT_EVEN 67
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#define CAM_CC_PLL0_OUT_ODD 68
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#define CAM_CC_PLL2 69
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#define CAM_CC_PLL3 70
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#define CAM_CC_PLL3_OUT_EVEN 71
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#define CAM_CC_PLL4 72
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#define CAM_CC_PLL4_OUT_EVEN 73
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#define CAM_CC_PLL5 74
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#define CAM_CC_PLL5_OUT_EVEN 75
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#define CAM_CC_SFE_LITE_0_CLK 76
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#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK 77
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#define CAM_CC_SFE_LITE_1_CLK 78
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#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK 79
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#define CAM_CC_SLEEP_CLK 80
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#define CAM_CC_SLEEP_CLK_SRC 81
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#define CAM_CC_SLOW_AHB_CLK_SRC 82
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#define CAM_CC_SM_OBS_CLK 83
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#define CAM_CC_XO_CLK_SRC 84
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#define CAM_CC_QDSS_DEBUG_XO_CLK 85
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/* CAM_CC power domains */
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#define CAM_CC_TITAN_TOP_GDSC 0
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/* CAM_CC resets */
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#define CAM_CC_ICP_BCR 0
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#define CAM_CC_IFE_0_BCR 1
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#define CAM_CC_IFE_1_BCR 2
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#define CAM_CC_IPE_0_BCR 3
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#define CAM_CC_SFE_LITE_0_BCR 4
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#define CAM_CC_SFE_LITE_1_BCR 5
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#endif

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