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Merge tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.7 kernel cycle. There are no core changes this time, only driver developments: - New driver for the Dialog Semiconductor DA9062 Power Management Integrated Circuit (PMIC). - Renesas SH-PFC has improved consistency, with group and register checks in the configuration checker. - New subdriver for the Qualcomm IPQ6018. - Add the RGMII pin control functionality to Qualcomm IPQ8064. - Performance and code quality cleanups in the Mediatek driver. - Improve the Broadcom BCM2835 support to cover all the GPIOs that exist in it. - The Allwinner/Sunxi driver properly masks non-wakeup IRQs on suspend. - Add some missing groups and functions to the Ingenic driver. - Convert some of the Freescale device tree bindings to use the new and all improved JSON YAML markup. - Refactorings and support for the SFIO/GPIO in the Tegra194 SoC driver. - Support high impedance mode in the Spreadtrum/Unisoc driver" * tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (64 commits) pinctrl: qcom: fix compilation error pinctrl: qcom: use scm_call to route GPIO irq to Apps pinctrl: sprd: Add pin high impedance mode support pinctrl: sprd: Use the correct pin output configuration pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 pinctrl: tegra: Renumber the GG.0 and GG.1 pins pinctrl: tegra: Do not add default pin range on Tegra194 pinctrl: tegra: Pass struct tegra_pmx for pin range check pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo pinctrl: tegra: Fix whitespace issues for improved readability pinctrl: mediatek: Use scnprintf() for avoiding potential buffer overflow pinctrl: freescale: drop the dependency on ARM64 for i.MX8M Revert "pinctrl: mvebu: armada-37xx: use use platform api" dt-bindings: pinctrl: at91: Fix a typo ("descibe") pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxm pinctrl: sprd: Fix the kconfig warning pinctrl: ingenic: add hdmi-ddc pin control group pinctrl: sirf/atlas7: Replace zero-length array with flexible-array member pinctrl: sprd: Allow the SPRD pinctrl driver building into a module pinctrl: Export some needed symbols at module load time ...
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‎Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt

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@@ -38,7 +38,7 @@ Bank: 3 (A, B and C)
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0xffffffff 0x7fff3ccf /* pioB */
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0xffffffff 0x007fffff /* pioC */
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For each peripheral/bank we will descibe in a u32 if a pin can be
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For each peripheral/bank we will describe in a u32 if a pin can be
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configured in it by putting 1 to the pin bit (1 << pin)
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Let's take the pioA on peripheral B

‎Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt

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‎Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml

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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX8MM IOMUX Controller
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maintainers:
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- Anson Huang <[email protected]>
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description:
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Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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properties:
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compatible:
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const: fsl,imx8mm-iomuxc
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last
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integer CONFIG is the pad setting value like pull-up on this pin. Please
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refer to i.MX8M Mini Reference Manual for detailed CONFIG settings.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-matrix
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- items:
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items:
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- description: |
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"mux_reg" indicates the offset of mux register.
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- description: |
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"conf_reg" indicates the offset of pad configuration register.
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- description: |
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"input_reg" indicates the offset of select input register.
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- description: |
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"mux_val" indicates the mux value to be applied.
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- description: |
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"input_val" indicates the select input value to be applied.
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- description: |
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"pad_setting" indicates the pad configuration value to be applied.
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required:
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- fsl,pins
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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# Pinmux controller node
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- |
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx8mm-iomuxc";
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reg = <0x30330000 0x10000>;
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pinctrl_uart2: uart2grp {
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fsl,pins =
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<0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
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<0x240 0x4A8 0x000 0x0 0x0 0x140>;
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};
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};
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...

‎Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt

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‎Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml

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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX8MN IOMUX Controller
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maintainers:
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- Anson Huang <[email protected]>
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description:
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Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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properties:
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compatible:
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const: fsl,imx8mn-iomuxc
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last
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integer CONFIG is the pad setting value like pull-up on this pin. Please
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refer to i.MX8M Nano Reference Manual for detailed CONFIG settings.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-matrix
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- items:
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items:
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- description: |
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"mux_reg" indicates the offset of mux register.
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- description: |
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"conf_reg" indicates the offset of pad configuration register.
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- description: |
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"input_reg" indicates the offset of select input register.
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- description: |
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"mux_val" indicates the mux value to be applied.
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- description: |
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"input_val" indicates the select input value to be applied.
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- description: |
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"pad_setting" indicates the pad configuration value to be applied.
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required:
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- fsl,pins
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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# Pinmux controller node
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- |
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx8mn-iomuxc";
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reg = <0x30330000 0x10000>;
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pinctrl_uart2: uart2grp {
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fsl,pins =
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<0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
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<0x240 0x4A8 0x000 0x0 0x0 0x140>;
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};
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};
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...

‎Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml

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Original file line numberDiff line numberDiff line change
@@ -30,15 +30,29 @@ patternProperties:
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properties:
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fsl,pins:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
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integer CONFIG is the pad setting value like pull-up on this pin. Please
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refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-matrix
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- items:
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items:
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- description: |
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"mux_reg" indicates the offset of mux register.
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- description: |
47+
"conf_reg" indicates the offset of pad configuration register.
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- description: |
49+
"input_reg" indicates the offset of select input register.
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- description: |
51+
"mux_val" indicates the mux value to be applied.
52+
- description: |
53+
"input_val" indicates the select input value to be applied.
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- description: |
55+
"pad_setting" indicates the pad configuration value to be applied.
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required:
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- fsl,pins
@@ -59,10 +73,9 @@ examples:
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reg = <0x30330000 0x10000>;
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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0x228 0x488 0x5F0 0x0 0x6 0x49
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0x228 0x488 0x000 0x0 0x0 0x49
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>;
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fsl,pins =
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<0x228 0x488 0x5F0 0x0 0x6 0x49>,
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<0x228 0x488 0x000 0x0 0x0 0x49>;
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};
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};
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‎Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt

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