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Merge tag 'omap-for-v5.4/fixes-rc1-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes
Fixes for omaps for v5.4-rc cycle Here are fixes for omaps to deal with few regressions, and to fix more boot time errors and warnings: - The recent ti-sysc interconnect target module driver changes had incorrect clock bits for both clocks and dts that cause warnings - For omap3-gta04, gpio changes caused the LCD to break a while back, and after discussing things the right fix is to set spi-cs-high - Recent omapdrm changes to use generic panels caused tfp410 to be disabled as we now must enable the generic support for it in defconfig - Recent omapdrm and backlight changes also finally made droid4 LCD to work, so let's enable it in the defconfig it can be used out of the box. This is not strictly a fix, but we still also have the older CONFIG_MFD_TI_LMU options available so this cuts down the confusion for trying to guess which display and which backlight is needed - Recent ti-sysc interconnect target module changes need the gpio module disabled on some boards, but this now needs to happen at the module level, not at the gpio driver level - Recent changes to probe system timers with ti-sysc caused warnings about mismatch in syconfig registers, so let's configure the option for RESET_STATUS as available in the TRMs - Recent changes to probe LCDC with ti-sysc caused warnings about mismatch in sysconfig registers, so let's configure the missing idlemodes for both platform data and dts as documented in TRMs - Since we moved mach-omap2 to probe with device tree, we've been getting voltage controller warnings. Turns out this code is no longer needed, so let's just remove omap2_set_init_voltage() to get rid of the pointless warnings - Configure am4372 dispc memory bandwidth to avoid underflow errors * tag 'omap-for-v5.4/fixes-rc1-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am4372: Set memory bandwidth limit for DISPC ARM: OMAP2+: Fix warnings with broken omap2_set_init_voltage() ARM: OMAP2+: Add missing LCDC midlemode for am335x ARM: OMAP2+: Fix missing reset done flag for am3 and am43 ARM: dts: Fix gpio0 flags for am335x-icev2 ARM: omap2plus_defconfig: Enable more droid4 devices as loadable modules ARM: omap2plus_defconfig: Enable DRM_TI_TFP410 DTS: ARM: gta04: introduce legacy spi-cs-high to make display work again ARM: dts: Fix wrong clocks for dra7 mcasp clk: ti: dra7: Fix mcasp8 clock bits Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2 parents cdee3b6 + f90ec6c commit bcec122

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+40
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‎arch/arm/boot/dts/am335x-icev2.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -432,7 +432,7 @@
432432
pinctrl-0 = <&mmc0_pins_default>;
433433
};
434434

435-
&gpio0 {
435+
&gpio0_target {
436436
/* Do not idle the GPIO used for holding the VTT regulator */
437437
ti,no-reset-on-init;
438438
ti,no-idle-on-init;

‎arch/arm/boot/dts/am33xx-l4.dtsi

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -127,7 +127,7 @@
127127
ranges = <0x0 0x5000 0x1000>;
128128
};
129129

130-
target-module@7000 { /* 0x44e07000, ap 14 20.0 */
130+
gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
131131
compatible = "ti,sysc-omap2", "ti,sysc";
132132
ti,hwmods = "gpio1";
133133
reg = <0x7000 0x4>,
@@ -2038,7 +2038,9 @@
20382038
reg = <0xe000 0x4>,
20392039
<0xe054 0x4>;
20402040
reg-names = "rev", "sysc";
2041-
ti,sysc-midle ;
2041+
ti,sysc-midle = <SYSC_IDLE_FORCE>,
2042+
<SYSC_IDLE_NO>,
2043+
<SYSC_IDLE_SMART>;
20422044
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
20432045
<SYSC_IDLE_NO>,
20442046
<SYSC_IDLE_SMART>;

‎arch/arm/boot/dts/am4372.dtsi

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -337,6 +337,8 @@
337337
ti,hwmods = "dss_dispc";
338338
clocks = <&disp_clk>;
339339
clock-names = "fck";
340+
341+
max-memory-bandwidth = <230000000>;
340342
};
341343

342344
rfbi: rfbi@4832a800 {

‎arch/arm/boot/dts/dra7-l4.dtsi

Lines changed: 21 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -2732,7 +2732,7 @@
27322732
interrupt-names = "tx", "rx";
27332733
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
27342734
dma-names = "tx", "rx";
2735-
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>,
2735+
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
27362736
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
27372737
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
27382738
clock-names = "fck", "ahclkx", "ahclkr";
@@ -2768,8 +2768,8 @@
27682768
interrupt-names = "tx", "rx";
27692769
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
27702770
dma-names = "tx", "rx";
2771-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>,
2772-
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2771+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2772+
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
27732773
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
27742774
clock-names = "fck", "ahclkx", "ahclkr";
27752775
status = "disabled";
@@ -2786,9 +2786,8 @@
27862786
<SYSC_IDLE_SMART>;
27872787
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
27882788
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2789-
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>,
2790-
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>;
2791-
clock-names = "fck", "ahclkx", "ahclkr";
2789+
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2790+
clock-names = "fck", "ahclkx";
27922791
#address-cells = <1>;
27932792
#size-cells = <1>;
27942793
ranges = <0x0 0x68000 0x2000>,
@@ -2804,7 +2803,7 @@
28042803
interrupt-names = "tx", "rx";
28052804
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
28062805
dma-names = "tx", "rx";
2807-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>,
2806+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
28082807
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
28092808
clock-names = "fck", "ahclkx";
28102809
status = "disabled";
@@ -2821,9 +2820,8 @@
28212820
<SYSC_IDLE_SMART>;
28222821
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
28232822
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2824-
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>,
2825-
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>;
2826-
clock-names = "fck", "ahclkx", "ahclkr";
2823+
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2824+
clock-names = "fck", "ahclkx";
28272825
#address-cells = <1>;
28282826
#size-cells = <1>;
28292827
ranges = <0x0 0x6c000 0x2000>,
@@ -2839,7 +2837,7 @@
28392837
interrupt-names = "tx", "rx";
28402838
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
28412839
dma-names = "tx", "rx";
2842-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>,
2840+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
28432841
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
28442842
clock-names = "fck", "ahclkx";
28452843
status = "disabled";
@@ -2856,9 +2854,8 @@
28562854
<SYSC_IDLE_SMART>;
28572855
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
28582856
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2859-
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>,
2860-
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>;
2861-
clock-names = "fck", "ahclkx", "ahclkr";
2857+
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2858+
clock-names = "fck", "ahclkx";
28622859
#address-cells = <1>;
28632860
#size-cells = <1>;
28642861
ranges = <0x0 0x70000 0x2000>,
@@ -2874,7 +2871,7 @@
28742871
interrupt-names = "tx", "rx";
28752872
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
28762873
dma-names = "tx", "rx";
2877-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>,
2874+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
28782875
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
28792876
clock-names = "fck", "ahclkx";
28802877
status = "disabled";
@@ -2891,9 +2888,8 @@
28912888
<SYSC_IDLE_SMART>;
28922889
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
28932890
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2894-
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>,
2895-
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>;
2896-
clock-names = "fck", "ahclkx", "ahclkr";
2891+
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2892+
clock-names = "fck", "ahclkx";
28972893
#address-cells = <1>;
28982894
#size-cells = <1>;
28992895
ranges = <0x0 0x74000 0x2000>,
@@ -2909,7 +2905,7 @@
29092905
interrupt-names = "tx", "rx";
29102906
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
29112907
dma-names = "tx", "rx";
2912-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>,
2908+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
29132909
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
29142910
clock-names = "fck", "ahclkx";
29152911
status = "disabled";
@@ -2926,9 +2922,8 @@
29262922
<SYSC_IDLE_SMART>;
29272923
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
29282924
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2929-
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>,
2930-
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>;
2931-
clock-names = "fck", "ahclkx", "ahclkr";
2925+
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2926+
clock-names = "fck", "ahclkx";
29322927
#address-cells = <1>;
29332928
#size-cells = <1>;
29342929
ranges = <0x0 0x78000 0x2000>,
@@ -2944,7 +2939,7 @@
29442939
interrupt-names = "tx", "rx";
29452940
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
29462941
dma-names = "tx", "rx";
2947-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>,
2942+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
29482943
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
29492944
clock-names = "fck", "ahclkx";
29502945
status = "disabled";
@@ -2961,9 +2956,8 @@
29612956
<SYSC_IDLE_SMART>;
29622957
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
29632958
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2964-
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>,
2965-
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>;
2966-
clock-names = "fck", "ahclkx", "ahclkr";
2959+
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2960+
clock-names = "fck", "ahclkx";
29672961
#address-cells = <1>;
29682962
#size-cells = <1>;
29692963
ranges = <0x0 0x7c000 0x2000>,
@@ -2979,7 +2973,7 @@
29792973
interrupt-names = "tx", "rx";
29802974
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
29812975
dma-names = "tx", "rx";
2982-
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>,
2976+
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
29832977
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
29842978
clock-names = "fck", "ahclkx";
29852979
status = "disabled";

‎arch/arm/boot/dts/omap3-gta04.dtsi

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,7 @@
124124
spi-max-frequency = <100000>;
125125
spi-cpol;
126126
spi-cpha;
127+
spi-cs-high;
127128

128129
backlight= <&backlight>;
129130
label = "lcd";

‎arch/arm/configs/omap2plus_defconfig

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -364,6 +364,7 @@ CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
364364
CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
365365
CONFIG_DRM_TILCDC=m
366366
CONFIG_DRM_PANEL_SIMPLE=m
367+
CONFIG_DRM_TI_TFP410=m
367368
CONFIG_FB=y
368369
CONFIG_FIRMWARE_EDID=y
369370
CONFIG_FB_MODE_HELPERS=y
@@ -423,6 +424,7 @@ CONFIG_USB_SERIAL_GENERIC=y
423424
CONFIG_USB_SERIAL_SIMPLE=m
424425
CONFIG_USB_SERIAL_FTDI_SIO=m
425426
CONFIG_USB_SERIAL_PL2303=m
427+
CONFIG_USB_SERIAL_OPTION=m
426428
CONFIG_USB_TEST=m
427429
CONFIG_NOP_USB_XCEIV=m
428430
CONFIG_AM335X_PHY_USB=m
@@ -460,6 +462,7 @@ CONFIG_MMC_SDHCI_OMAP=y
460462
CONFIG_NEW_LEDS=y
461463
CONFIG_LEDS_CLASS=m
462464
CONFIG_LEDS_CPCAP=m
465+
CONFIG_LEDS_LM3532=m
463466
CONFIG_LEDS_GPIO=m
464467
CONFIG_LEDS_PCA963X=m
465468
CONFIG_LEDS_PWM=m

‎arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -763,7 +763,8 @@ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
763763
.rev_offs = 0x0000,
764764
.sysc_offs = 0x0010,
765765
.syss_offs = 0x0014,
766-
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
766+
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
767+
SYSC_HAS_RESET_STATUS,
767768
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
768769
SIDLE_SMART_WKUP),
769770
.sysc_fields = &omap_hwmod_sysc_type2,

‎arch/arm/mach-omap2/omap_hwmod_33xx_data.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -231,8 +231,9 @@ static struct omap_hwmod am33xx_control_hwmod = {
231231
static struct omap_hwmod_class_sysconfig lcdc_sysc = {
232232
.rev_offs = 0x0,
233233
.sysc_offs = 0x54,
234-
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
235-
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
234+
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE,
235+
.idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
236+
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART,
236237
.sysc_fields = &omap_hwmod_sysc_type2,
237238
};
238239

‎arch/arm/mach-omap2/pm.c

Lines changed: 0 additions & 100 deletions
Original file line numberDiff line numberDiff line change
@@ -74,83 +74,6 @@ int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
7474
return 0;
7575
}
7676

77-
/*
78-
* This API is to be called during init to set the various voltage
79-
* domains to the voltage as per the opp table. Typically we boot up
80-
* at the nominal voltage. So this function finds out the rate of
81-
* the clock associated with the voltage domain, finds out the correct
82-
* opp entry and sets the voltage domain to the voltage specified
83-
* in the opp entry
84-
*/
85-
static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
86-
const char *oh_name)
87-
{
88-
struct voltagedomain *voltdm;
89-
struct clk *clk;
90-
struct dev_pm_opp *opp;
91-
unsigned long freq, bootup_volt;
92-
struct device *dev;
93-
94-
if (!vdd_name || !clk_name || !oh_name) {
95-
pr_err("%s: invalid parameters\n", __func__);
96-
goto exit;
97-
}
98-
99-
if (!strncmp(oh_name, "mpu", 3))
100-
/*
101-
* All current OMAPs share voltage rail and clock
102-
* source, so CPU0 is used to represent the MPU-SS.
103-
*/
104-
dev = get_cpu_device(0);
105-
else
106-
dev = omap_device_get_by_hwmod_name(oh_name);
107-
108-
if (IS_ERR(dev)) {
109-
pr_err("%s: Unable to get dev pointer for hwmod %s\n",
110-
__func__, oh_name);
111-
goto exit;
112-
}
113-
114-
voltdm = voltdm_lookup(vdd_name);
115-
if (!voltdm) {
116-
pr_err("%s: unable to get vdd pointer for vdd_%s\n",
117-
__func__, vdd_name);
118-
goto exit;
119-
}
120-
121-
clk = clk_get(NULL, clk_name);
122-
if (IS_ERR(clk)) {
123-
pr_err("%s: unable to get clk %s\n", __func__, clk_name);
124-
goto exit;
125-
}
126-
127-
freq = clk_get_rate(clk);
128-
clk_put(clk);
129-
130-
opp = dev_pm_opp_find_freq_ceil(dev, &freq);
131-
if (IS_ERR(opp)) {
132-
pr_err("%s: unable to find boot up OPP for vdd_%s\n",
133-
__func__, vdd_name);
134-
goto exit;
135-
}
136-
137-
bootup_volt = dev_pm_opp_get_voltage(opp);
138-
dev_pm_opp_put(opp);
139-
140-
if (!bootup_volt) {
141-
pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
142-
__func__, vdd_name);
143-
goto exit;
144-
}
145-
146-
voltdm_scale(voltdm, bootup_volt);
147-
return 0;
148-
149-
exit:
150-
pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
151-
return -EINVAL;
152-
}
153-
15477
#ifdef CONFIG_SUSPEND
15578
static int omap_pm_enter(suspend_state_t suspend_state)
15679
{
@@ -208,25 +131,6 @@ void omap_common_suspend_init(void *pm_suspend)
208131
}
209132
#endif /* CONFIG_SUSPEND */
210133

211-
static void __init omap3_init_voltages(void)
212-
{
213-
if (!soc_is_omap34xx())
214-
return;
215-
216-
omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
217-
omap2_set_init_voltage("core", "l3_ick", "l3_main");
218-
}
219-
220-
static void __init omap4_init_voltages(void)
221-
{
222-
if (!soc_is_omap44xx())
223-
return;
224-
225-
omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
226-
omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
227-
omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
228-
}
229-
230134
int __maybe_unused omap_pm_nop_init(void)
231135
{
232136
return 0;
@@ -246,10 +150,6 @@ int __init omap2_common_pm_late_init(void)
246150
omap4_twl_init();
247151
omap_voltage_late_init();
248152

249-
/* Initialize the voltages */
250-
omap3_init_voltages();
251-
omap4_init_voltages();
252-
253153
/* Smartreflex device init */
254154
omap_devinit_smartreflex();
255155

‎drivers/clk/ti/clk-7xx.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -683,7 +683,7 @@ static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst
683683
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
684684
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
685685
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
686-
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
686+
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
687687
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
688688
{ DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
689689
{ DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
@@ -828,8 +828,8 @@ static struct ti_dt_clk dra7xx_clks[] = {
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DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
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DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
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DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
831-
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"),
832-
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"),
831+
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
832+
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
833833
DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
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DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
835835
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),

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