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drivers/gpu/drm/amd/display/dc/hwss/dcn31 Expand file tree Collapse file tree 1 file changed +6
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lines changed Original file line number Diff line number Diff line change @@ -519,15 +519,18 @@ static void dcn31_reset_back_end_for_pipe(
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dc -> hwss .set_abm_immediate_disable (pipe_ctx );
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- if ((!pipe_ctx -> stream -> dpms_off || pipe_ctx -> stream -> link -> link_status .link_active )
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- && pipe_ctx -> stream -> sink && pipe_ctx -> stream -> sink -> edid_caps .panel_patch .blankstream_before_otg_off ) {
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+ link = pipe_ctx -> stream -> link ;
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+
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+ if ((!pipe_ctx -> stream -> dpms_off || link -> link_status .link_active ) &&
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+ (link -> connector_signal == SIGNAL_TYPE_EDP ))
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dc -> hwss .blank_stream (pipe_ctx );
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- }
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pipe_ctx -> stream_res .tg -> funcs -> set_dsc_config (
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pipe_ctx -> stream_res .tg ,
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OPTC_DSC_DISABLED , 0 , 0 );
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+
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pipe_ctx -> stream_res .tg -> funcs -> disable_crtc (pipe_ctx -> stream_res .tg );
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+
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pipe_ctx -> stream_res .tg -> funcs -> enable_optc_clock (pipe_ctx -> stream_res .tg , false);
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if (pipe_ctx -> stream_res .tg -> funcs -> set_odm_bypass )
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pipe_ctx -> stream_res .tg -> funcs -> set_odm_bypass (
@@ -539,7 +542,6 @@ static void dcn31_reset_back_end_for_pipe(
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pipe_ctx -> stream_res .tg -> funcs -> set_drr (
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pipe_ctx -> stream_res .tg , NULL );
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- link = pipe_ctx -> stream -> link ;
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/* DPMS may already disable or */
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/* dpms_off status is incorrect due to fastboot
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* feature. When system resume from S4 with second
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