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Lee Jonesbebarino
Lee Jones
authored and
bebarino
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clk: zynq: clkc: Remove various instances of an unused variable 'clk'
Fixes the following W=1 kernel build warning(s): drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_fclk’: drivers/clk/zynq/clkc.c:106:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_periph_clk’: drivers/clk/zynq/clkc.c:179:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] drivers/clk/zynq/clkc.c: In function ‘zynq_clk_setup’: drivers/clk/zynq/clkc.c:220:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Michal Simek <[email protected]> Cc: "Sören Brinkmann" <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/zynq/clkc.c

Lines changed: 35 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,6 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
103103
const char *clk_name, void __iomem *fclk_ctrl_reg,
104104
const char **parents, int enable)
105105
{
106-
struct clk *clk;
107106
u32 enable_reg;
108107
char *mux_name;
109108
char *div0_name;
@@ -131,15 +130,15 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
131130
if (!div1_name)
132131
goto err_div1_name;
133132

134-
clk = clk_register_mux(NULL, mux_name, parents, 4,
133+
clk_register_mux(NULL, mux_name, parents, 4,
135134
CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
136135
fclk_lock);
137136

138-
clk = clk_register_divider(NULL, div0_name, mux_name,
137+
clk_register_divider(NULL, div0_name, mux_name,
139138
0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
140139
CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
141140

142-
clk = clk_register_divider(NULL, div1_name, div0_name,
141+
clk_register_divider(NULL, div1_name, div0_name,
143142
CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
144143
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
145144
fclk_lock);
@@ -176,7 +175,6 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
176175
const char *clk_name1, void __iomem *clk_ctrl,
177176
const char **parents, unsigned int two_gates)
178177
{
179-
struct clk *clk;
180178
char *mux_name;
181179
char *div_name;
182180
spinlock_t *lock;
@@ -189,10 +187,10 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
189187
mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
190188
div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
191189

192-
clk = clk_register_mux(NULL, mux_name, parents, 4,
190+
clk_register_mux(NULL, mux_name, parents, 4,
193191
CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
194192

195-
clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
193+
clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
196194
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
197195

198196
clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
@@ -217,7 +215,6 @@ static void __init zynq_clk_setup(struct device_node *np)
217215
int i;
218216
u32 tmp;
219217
int ret;
220-
struct clk *clk;
221218
char *clk_name;
222219
unsigned int fclk_enable = 0;
223220
const char *clk_output_name[clk_max];
@@ -257,51 +254,51 @@ static void __init zynq_clk_setup(struct device_node *np)
257254
ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
258255

259256
/* PLLs */
260-
clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
257+
clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
261258
SLCR_PLL_STATUS, 0, &armpll_lock);
262259
clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
263260
armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
264261
SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
265262

266-
clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
263+
clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
267264
SLCR_PLL_STATUS, 1, &ddrpll_lock);
268265
clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
269266
ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
270267
SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
271268

272-
clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
269+
clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
273270
SLCR_PLL_STATUS, 2, &iopll_lock);
274271
clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
275272
iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
276273
SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
277274

278275
/* CPU clocks */
279276
tmp = readl(SLCR_621_TRUE) & 1;
280-
clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
277+
clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
281278
CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
282279
&armclk_lock);
283-
clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
280+
clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
284281
SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
285282
CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
286283

287284
clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
288285
"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
289286
SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
290287

291-
clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
288+
clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
292289
1, 2);
293290
clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
294291
"cpu_3or2x_div", CLK_IGNORE_UNUSED,
295292
SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
296293

297-
clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
294+
clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
298295
2 + tmp);
299296
clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
300297
"cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
301298
26, 0, &armclk_lock);
302299
clk_prepare_enable(clks[cpu_2x]);
303300

304-
clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
301+
clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
305302
4 + 2 * tmp);
306303
clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
307304
"cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
@@ -324,23 +321,23 @@ static void __init zynq_clk_setup(struct device_node *np)
324321
&swdtclk_lock);
325322

326323
/* DDR clocks */
327-
clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
324+
clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
328325
SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
329326
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
330327
clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
331328
"ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
332329
clk_prepare_enable(clks[ddr2x]);
333-
clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
330+
clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
334331
SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
335332
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
336333
clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
337334
"ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
338335
clk_prepare_enable(clks[ddr3x]);
339336

340-
clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
337+
clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
341338
SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
342339
CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
343-
clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
340+
clk_register_divider(NULL, "dci_div1", "dci_div0",
344341
CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
345342
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
346343
&dciclk_lock);
@@ -385,17 +382,17 @@ static void __init zynq_clk_setup(struct device_node *np)
385382
gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
386383
idx);
387384
}
388-
clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
385+
clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
389386
CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
390387
&gem0clk_lock);
391-
clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
388+
clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
392389
SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
393390
CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
394-
clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
391+
clk_register_divider(NULL, "gem0_div1", "gem0_div0",
395392
CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
396393
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
397394
&gem0clk_lock);
398-
clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
395+
clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
399396
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
400397
SLCR_GEM0_CLK_CTRL, 6, 1, 0,
401398
&gem0clk_lock);
@@ -410,17 +407,17 @@ static void __init zynq_clk_setup(struct device_node *np)
410407
gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
411408
idx);
412409
}
413-
clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
410+
clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
414411
CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
415412
&gem1clk_lock);
416-
clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
413+
clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
417414
SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
418415
CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
419-
clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
416+
clk_register_divider(NULL, "gem1_div1", "gem1_div0",
420417
CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
421418
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
422419
&gem1clk_lock);
423-
clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
420+
clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
424421
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
425422
SLCR_GEM1_CLK_CTRL, 6, 1, 0,
426423
&gem1clk_lock);
@@ -442,27 +439,27 @@ static void __init zynq_clk_setup(struct device_node *np)
442439
can_mio_mux_parents[i] = dummy_nm;
443440
}
444441
kfree(clk_name);
445-
clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
442+
clk_register_mux(NULL, "can_mux", periph_parents, 4,
446443
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
447444
&canclk_lock);
448-
clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
445+
clk_register_divider(NULL, "can_div0", "can_mux", 0,
449446
SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
450447
CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
451-
clk = clk_register_divider(NULL, "can_div1", "can_div0",
448+
clk_register_divider(NULL, "can_div1", "can_div0",
452449
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
453450
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
454451
&canclk_lock);
455-
clk = clk_register_gate(NULL, "can0_gate", "can_div1",
452+
clk_register_gate(NULL, "can0_gate", "can_div1",
456453
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
457454
&canclk_lock);
458-
clk = clk_register_gate(NULL, "can1_gate", "can_div1",
455+
clk_register_gate(NULL, "can1_gate", "can_div1",
459456
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
460457
&canclk_lock);
461-
clk = clk_register_mux(NULL, "can0_mio_mux",
458+
clk_register_mux(NULL, "can0_mio_mux",
462459
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
463460
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
464461
&canmioclk_lock);
465-
clk = clk_register_mux(NULL, "can1_mio_mux",
462+
clk_register_mux(NULL, "can1_mio_mux",
466463
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
467464
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
468465
0, &canmioclk_lock);
@@ -482,13 +479,13 @@ static void __init zynq_clk_setup(struct device_node *np)
482479
dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
483480
idx);
484481
}
485-
clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
482+
clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
486483
CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
487484
&dbgclk_lock);
488-
clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
485+
clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
489486
SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
490487
CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
491-
clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
488+
clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
492489
CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
493490
&dbgclk_lock);
494491
clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],

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