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Merge tag 'amd-drm-fixes-5.15-2021-10-06' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-5.15-2021-10-06: amdgpu: - DCN 3.1 DP alt mode fixes - S0ix gfxoff fix - Fix DRM_AMD_DC_SI dependencies - PCIe DPC handling fix - DCN 3.1 scaling fix - Documentation fix amdkfd: - Fix potential memory leak - IOMMUv2 init fixes Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents b28a130 + 5a1fef0 commit bf79045

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+142
-26
lines changed

14 files changed

+142
-26
lines changed

‎Documentation/gpu/amdgpu.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -300,8 +300,8 @@ pcie_replay_count
300300
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
301301
:doc: pcie_replay_count
302302

303-
+GPU SmartShift Information
304-
============================
303+
GPU SmartShift Information
304+
==========================
305305

306306
GPU SmartShift information via sysfs
307307

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1087,6 +1087,7 @@ struct amdgpu_device {
10871087

10881088
bool no_hw_access;
10891089
struct pci_saved_state *pci_state;
1090+
pci_channel_state_t pci_channel_state;
10901091

10911092
struct amdgpu_reset_control *reset_cntl;
10921093
};

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -563,6 +563,7 @@ kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
563563

564564
dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
565565
sg_free_table(ttm->sg);
566+
kfree(ttm->sg);
566567
ttm->sg = NULL;
567568
}
568569

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2394,10 +2394,6 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
23942394
if (r)
23952395
goto init_failed;
23962396

2397-
r = amdgpu_amdkfd_resume_iommu(adev);
2398-
if (r)
2399-
goto init_failed;
2400-
24012397
r = amdgpu_device_ip_hw_init_phase1(adev);
24022398
if (r)
24032399
goto init_failed;
@@ -2436,6 +2432,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
24362432
if (!adev->gmc.xgmi.pending_reset)
24372433
amdgpu_amdkfd_device_init(adev);
24382434

2435+
r = amdgpu_amdkfd_resume_iommu(adev);
2436+
if (r)
2437+
goto init_failed;
2438+
24392439
amdgpu_fru_get_product_info(adev);
24402440

24412441
init_failed:
@@ -5399,6 +5399,8 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta
53995399
return PCI_ERS_RESULT_DISCONNECT;
54005400
}
54015401

5402+
adev->pci_channel_state = state;
5403+
54025404
switch (state) {
54035405
case pci_channel_io_normal:
54045406
return PCI_ERS_RESULT_CAN_RECOVER;
@@ -5541,6 +5543,10 @@ void amdgpu_pci_resume(struct pci_dev *pdev)
55415543

55425544
DRM_INFO("PCI error: resume callback!!\n");
55435545

5546+
/* Only continue execution for the case of pci_channel_io_frozen */
5547+
if (adev->pci_channel_state != pci_channel_io_frozen)
5548+
return;
5549+
55445550
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
55455551
struct amdgpu_ring *ring = adev->rings[i];
55465552

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,8 @@
3131
/* delay 0.1 second to enable gfx off feature */
3232
#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
3333

34+
#define GFX_OFF_NO_DELAY 0
35+
3436
/*
3537
* GPU GFX IP block helpers function.
3638
*/
@@ -558,6 +560,8 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
558560

559561
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
560562
{
563+
unsigned long delay = GFX_OFF_DELAY_ENABLE;
564+
561565
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
562566
return;
563567

@@ -573,8 +577,14 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
573577

574578
adev->gfx.gfx_off_req_count--;
575579

576-
if (adev->gfx.gfx_off_req_count == 0 && !adev->gfx.gfx_off_state)
577-
schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE);
580+
if (adev->gfx.gfx_off_req_count == 0 &&
581+
!adev->gfx.gfx_off_state) {
582+
/* If going to s2idle, no need to wait */
583+
if (adev->in_s0ix)
584+
delay = GFX_OFF_NO_DELAY;
585+
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
586+
delay);
587+
}
578588
} else {
579589
if (adev->gfx.gfx_off_req_count == 0) {
580590
cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);

‎drivers/gpu/drm/amd/amdkfd/kfd_device.c

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1085,18 +1085,12 @@ static int kfd_resume(struct kfd_dev *kfd)
10851085
int err = 0;
10861086

10871087
err = kfd->dqm->ops.start(kfd->dqm);
1088-
if (err) {
1088+
if (err)
10891089
dev_err(kfd_device,
10901090
"Error starting queue manager for device %x:%x\n",
10911091
kfd->pdev->vendor, kfd->pdev->device);
1092-
goto dqm_start_error;
1093-
}
10941092

10951093
return err;
1096-
1097-
dqm_start_error:
1098-
kfd_iommu_suspend(kfd);
1099-
return err;
11001094
}
11011095

11021096
static inline void kfd_queue_work(struct workqueue_struct *wq,

‎drivers/gpu/drm/amd/display/Kconfig

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@ config DRM_AMD_DC_HDCP
2525

2626
config DRM_AMD_DC_SI
2727
bool "AMD DC support for Southern Islands ASICs"
28+
depends on DRM_AMDGPU_SI
29+
depends on DRM_AMD_DC
2830
default n
2931
help
3032
Choose this option to enable new AMD DC support for SI asics

‎drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1306,12 +1306,6 @@ static void override_training_settings(
13061306
{
13071307
uint32_t lane;
13081308

1309-
/* Override link settings */
1310-
if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1311-
lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1312-
if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1313-
lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1314-
13151309
/* Override link spread */
13161310
if (!link->dp_ss_off && overrides->downspread != NULL)
13171311
lt_settings->link_settings.link_spread = *overrides->downspread ?

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ struct dcn10_link_enc_registers {
118118
uint32_t RDPCSTX_PHY_CNTL4;
119119
uint32_t RDPCSTX_PHY_CNTL5;
120120
uint32_t RDPCSTX_PHY_CNTL6;
121+
uint32_t RDPCSPIPE_PHY_CNTL6;
121122
uint32_t RDPCSTX_PHY_CNTL7;
122123
uint32_t RDPCSTX_PHY_CNTL8;
123124
uint32_t RDPCSTX_PHY_CNTL9;

‎drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c

Lines changed: 64 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737

3838
#include "link_enc_cfg.h"
3939
#include "dc_dmub_srv.h"
40+
#include "dal_asic_id.h"
4041

4142
#define CTX \
4243
enc10->base.ctx
@@ -62,6 +63,10 @@
6263
#define AUX_REG_WRITE(reg_name, val) \
6364
dm_write_reg(CTX, AUX_REG(reg_name), val)
6465

66+
#ifndef MIN
67+
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
68+
#endif
69+
6570
void dcn31_link_encoder_set_dio_phy_mux(
6671
struct link_encoder *enc,
6772
enum encoder_type_select sel,
@@ -215,8 +220,8 @@ static const struct link_encoder_funcs dcn31_link_enc_funcs = {
215220
.fec_is_active = enc2_fec_is_active,
216221
.get_dig_frontend = dcn10_get_dig_frontend,
217222
.get_dig_mode = dcn10_get_dig_mode,
218-
.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
219-
.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
223+
.is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
224+
.get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
220225
.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
221226
};
222227

@@ -404,3 +409,60 @@ void dcn31_link_encoder_disable_output(
404409
}
405410
}
406411

412+
bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
413+
{
414+
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
415+
uint32_t dp_alt_mode_disable;
416+
bool is_usb_c_alt_mode = false;
417+
418+
if (enc->features.flags.bits.DP_IS_USB_C) {
419+
if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
420+
// [Note] no need to check hw_internal_rev once phy mux selection is ready
421+
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
422+
} else {
423+
/*
424+
* B0 phys use a new set of registers to check whether alt mode is disabled.
425+
* if value == 1 alt mode is disabled, otherwise it is enabled.
426+
*/
427+
if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
428+
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
429+
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
430+
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
431+
} else {
432+
// [Note] need to change TRANSMITTER_UNIPHY_C/D to F/G once phy mux selection is ready
433+
REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
434+
}
435+
}
436+
437+
is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
438+
}
439+
440+
return is_usb_c_alt_mode;
441+
}
442+
443+
void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
444+
struct dc_link_settings *link_settings)
445+
{
446+
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
447+
uint32_t is_in_usb_c_dp4_mode = 0;
448+
449+
dcn10_link_encoder_get_max_link_cap(enc, link_settings);
450+
451+
/* in usb c dp2 mode, max lane count is 2 */
452+
if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
453+
if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
454+
// [Note] no need to check hw_internal_rev once phy mux selection is ready
455+
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
456+
} else {
457+
if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
458+
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
459+
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
460+
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
461+
} else {
462+
REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
463+
}
464+
}
465+
if (!is_in_usb_c_dp4_mode)
466+
link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
467+
}
468+
}

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