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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Freescale Management Complex |
| 8 | + |
| 9 | +maintainers: |
| 10 | + |
| 11 | + |
| 12 | +description: | |
| 13 | + The Freescale Management Complex (fsl-mc) is a hardware resource |
| 14 | + manager that manages specialized hardware objects used in |
| 15 | + network-oriented packet processing applications. After the fsl-mc |
| 16 | + block is enabled, pools of hardware resources are available, such as |
| 17 | + queues, buffer pools, I/O interfaces. These resources are building |
| 18 | + blocks that can be used to create functional hardware objects/devices |
| 19 | + such as network interfaces, crypto accelerator instances, L2 switches, |
| 20 | + etc. |
| 21 | +
|
| 22 | + For an overview of the DPAA2 architecture and fsl-mc bus see: |
| 23 | + Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst |
| 24 | +
|
| 25 | + As described in the above overview, all DPAA2 objects in a DPRC share the |
| 26 | + same hardware "isolation context" and a 10-bit value called an ICID |
| 27 | + (isolation context id) is expressed by the hardware to identify |
| 28 | + the requester. |
| 29 | +
|
| 30 | + The generic 'iommus' property is insufficient to describe the relationship |
| 31 | + between ICIDs and IOMMUs, so an iommu-map property is used to define |
| 32 | + the set of possible ICIDs under a root DPRC and how they map to |
| 33 | + an IOMMU. |
| 34 | +
|
| 35 | + For generic IOMMU bindings, see |
| 36 | + Documentation/devicetree/bindings/iommu/iommu.txt. |
| 37 | +
|
| 38 | + For arm-smmu binding, see: |
| 39 | + Documentation/devicetree/bindings/iommu/arm,smmu.yaml. |
| 40 | +
|
| 41 | + The MSI writes are accompanied by sideband data which is derived from the ICID. |
| 42 | + The msi-map property is used to associate the devices with both the ITS |
| 43 | + controller and the sideband data which accompanies the writes. |
| 44 | +
|
| 45 | + For generic MSI bindings, see |
| 46 | + Documentation/devicetree/bindings/interrupt-controller/msi.txt. |
| 47 | +
|
| 48 | + For GICv3 and GIC ITS bindings, see: |
| 49 | + Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml. |
| 50 | +
|
| 51 | +properties: |
| 52 | + compatible: |
| 53 | + enum: |
| 54 | + - fsl,qoriq-mc |
| 55 | + description: |
| 56 | + Must be "fsl,qoriq-mc". A Freescale Management Complex |
| 57 | + compatible with this binding must have Block Revision |
| 58 | + Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in |
| 59 | + the MC control register region. |
| 60 | + |
| 61 | + reg: |
| 62 | + items: |
| 63 | + - description: |
| 64 | + the first region is the command portal for the |
| 65 | + this machine and must always be present |
| 66 | + |
| 67 | + - description: |
| 68 | + the second region is the MC control registers. This |
| 69 | + region may not be present in some scenarios, such |
| 70 | + as in the device tree presented to a virtual machine. |
| 71 | + |
| 72 | + ranges: |
| 73 | + description: | |
| 74 | + A standard property. Defines the mapping between the child |
| 75 | + MC address space and the parent system address space. |
| 76 | +
|
| 77 | + The MC address space is defined by 3 components: |
| 78 | + <region type> <offset hi> <offset lo> |
| 79 | +
|
| 80 | + Valid values for region type are |
| 81 | + 0x0 - MC portals |
| 82 | + 0x1 - QBMAN portals |
| 83 | +
|
| 84 | + "#address-cells": |
| 85 | + const: 3 |
| 86 | + |
| 87 | + "#size-cells": |
| 88 | + const: 1 |
| 89 | + |
| 90 | + iommu-map: |
| 91 | + description: | |
| 92 | + Maps an ICID to an IOMMU and associated iommu-specifier |
| 93 | + data. |
| 94 | +
|
| 95 | + The property is an arbitrary number of tuples of |
| 96 | + (icid-base,iommu,iommu-base,length). |
| 97 | +
|
| 98 | + Any ICID i in the interval [icid-base, icid-base + length) is |
| 99 | + associated with the listed IOMMU, with the iommu-specifier |
| 100 | + (i - icid-base + iommu-base). |
| 101 | +
|
| 102 | + msi-map: |
| 103 | + description: | |
| 104 | + Maps an ICID to a GIC ITS and associated msi-specifier |
| 105 | + data. |
| 106 | +
|
| 107 | + The property is an arbitrary number of tuples of |
| 108 | + (icid-base,gic-its,msi-base,length). |
| 109 | +
|
| 110 | + Any ICID in the interval [icid-base, icid-base + length) is |
| 111 | + associated with the listed GIC ITS, with the msi-specifier |
| 112 | + (i - icid-base + msi-base). |
| 113 | +
|
| 114 | + msi-parent: |
| 115 | + deprecated: true |
| 116 | + $ref: /schemas/types.yaml#/definitions/phandle |
| 117 | + description: |
| 118 | + Describes the MSI controller node handling message |
| 119 | + interrupts for the MC. When there is no translation |
| 120 | + between the ICID and deviceID this property can be used |
| 121 | + to describe the MSI controller used by the devices on the |
| 122 | + mc-bus. |
| 123 | + The use of this property for mc-bus is deprecated. Please |
| 124 | + use msi-map. |
| 125 | + |
| 126 | + dma-coherent: true |
| 127 | + |
| 128 | + dpmacs: |
| 129 | + type: object |
| 130 | + description: |
| 131 | + The fsl-mc node may optionally have dpmac sub-nodes that describe |
| 132 | + the relationship between the Ethernet MACs which belong to the MC |
| 133 | + and the Ethernet PHYs on the system board. |
| 134 | + |
| 135 | + properties: |
| 136 | + "#address-cells": |
| 137 | + const: 1 |
| 138 | + |
| 139 | + "#size-cells": |
| 140 | + const: 0 |
| 141 | + |
| 142 | + patternProperties: |
| 143 | + '^ethernet@[a-f0-9]+$': |
| 144 | + $ref: /schemas/net/fsl,qoriq-mc-dpmac.yaml |
| 145 | + |
| 146 | + additionalProperties: false |
| 147 | + |
| 148 | +required: |
| 149 | + - compatible |
| 150 | + - reg |
| 151 | + - ranges |
| 152 | + - "#address-cells" |
| 153 | + - "#size-cells" |
| 154 | + |
| 155 | +additionalProperties: false |
| 156 | + |
| 157 | +examples: |
| 158 | + - | |
| 159 | + fsl-mc@80c000000 { |
| 160 | + compatible = "fsl,qoriq-mc"; |
| 161 | + reg = <0x0c000000 0x40>, /* MC portal base */ |
| 162 | + <0x08340000 0x40000>; /* MC control reg */ |
| 163 | + /* |
| 164 | + * Region type 0x0 - MC portals |
| 165 | + * Region type 0x1 - QBMAN portals |
| 166 | + */ |
| 167 | + ranges = <0x0 0x0 0x8 0x0c000000 0x4000000 |
| 168 | + 0x1 0x0 0x8 0x18000000 0x8000000>; |
| 169 | + |
| 170 | + /* define map for ICIDs 23-64 */ |
| 171 | + iommu-map = <23 &smmu 23 41>; |
| 172 | + /* define msi map for ICIDs 23-64 */ |
| 173 | + msi-map = <23 &its 23 41>; |
| 174 | + #address-cells = <3>; |
| 175 | + #size-cells = <1>; |
| 176 | +
|
| 177 | + dpmacs { |
| 178 | + #address-cells = <1>; |
| 179 | + #size-cells = <0>; |
| 180 | +
|
| 181 | + ethernet@1 { |
| 182 | + compatible = "fsl,qoriq-mc-dpmac"; |
| 183 | + reg = <1>; |
| 184 | + phy-handle = <&mdio0_phy0>; |
| 185 | + }; |
| 186 | + }; |
| 187 | + }; |
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