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Merge tag 'asahi-soc-dt-5.16-v2' of https://github.com/AsahiLinux/linux into arm/dt
Apple SoC DT updates for 5.16. Adds pinctrl and PCIe nodes. * tag 'asahi-soc-dt-5.16-v2' of https://github.com/AsahiLinux/linux: arm64: dts: apple: j274: Expose PCI node for the Ethernet MAC address arm64: dts: apple: t8103: Add root port interrupt routing arm64: dts: apple: t8103: Add PCIe DARTs arm64: apple: Add PCIe node arm64: apple: Add pinctrl nodes Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎arch/arm64/boot/dts/apple/t8103-j274.dts

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aliases {
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serial0 = &serial0;
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ethernet0 = &ethernet0;
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};
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chosen {
@@ -43,3 +44,25 @@
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&serial0 {
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status = "okay";
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};
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/*
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* Force the bus number assignments so that we can declare some of the
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* on-board devices and properties that are populated by the bootloader
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* (such as MAC addresses).
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*/
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&port00 {
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bus-range = <1 1>;
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};
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&port01 {
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bus-range = <2 2>;
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};
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&port02 {
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bus-range = <3 3>;
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ethernet0: pci@0,0 {
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reg = <0x30000 0x0 0x0 0x0 0x0>;
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/* To be filled by the loader */
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local-mac-address = [00 10 18 00 00 00];
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};
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};

‎arch/arm64/boot/dts/apple/t8103.dtsi

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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/apple.h>
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/ {
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compatible = "apple,t8103", "apple,arm-platform";
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interrupt-controller;
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reg = <0x2 0x3b100000 0x0 0x8000>;
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};
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pinctrl_ap: pinctrl@23c100000 {
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compatible = "apple,t8103-pinctrl", "apple,pinctrl";
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reg = <0x2 0x3c100000 0x0 0x100000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_ap 0 0 212>;
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apple,npins = <212>;
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interrupt-controller;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
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pcie_pins: pcie-pins {
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pinmux = <APPLE_PINMUX(150, 1)>,
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<APPLE_PINMUX(151, 1)>,
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<APPLE_PINMUX(32, 1)>;
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};
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};
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pinctrl_aop: pinctrl@24a820000 {
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compatible = "apple,t8103-pinctrl", "apple,pinctrl";
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reg = <0x2 0x4a820000 0x0 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aop 0 0 42>;
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apple,npins = <42>;
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interrupt-controller;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_nub: pinctrl@23d1f0000 {
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compatible = "apple,t8103-pinctrl", "apple,pinctrl";
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reg = <0x2 0x3d1f0000 0x0 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_nub 0 0 23>;
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apple,npins = <23>;
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interrupt-controller;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_smc: pinctrl@23e820000 {
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compatible = "apple,t8103-pinctrl", "apple,pinctrl";
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reg = <0x2 0x3e820000 0x0 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_smc 0 0 16>;
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apple,npins = <16>;
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interrupt-controller;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
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};
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pcie0_dart_0: dart@681008000 {
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compatible = "apple,t8103-dart";
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reg = <0x6 0x81008000 0x0 0x4000>;
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#iommu-cells = <1>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
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};
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pcie0_dart_1: dart@682008000 {
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compatible = "apple,t8103-dart";
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reg = <0x6 0x82008000 0x0 0x4000>;
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#iommu-cells = <1>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
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};
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pcie0_dart_2: dart@683008000 {
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compatible = "apple,t8103-dart";
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reg = <0x6 0x83008000 0x0 0x4000>;
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#iommu-cells = <1>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
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};
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pcie0: pcie@690000000 {
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compatible = "apple,t8103-pcie", "apple,pcie";
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device_type = "pci";
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reg = <0x6 0x90000000 0x0 0x1000000>,
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<0x6 0x80000000 0x0 0x100000>,
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<0x6 0x81000000 0x0 0x4000>,
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<0x6 0x82000000 0x0 0x4000>,
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<0x6 0x83000000 0x0 0x4000>;
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reg-names = "config", "rc", "port0", "port1", "port2";
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
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msi-controller;
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msi-parent = <&pcie0>;
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msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
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iommu-map = <0x100 &pcie0_dart_0 1 1>,
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<0x200 &pcie0_dart_1 1 1>,
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<0x300 &pcie0_dart_2 1 1>;
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iommu-map-mask = <0xff00>;
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bus-range = <0 3>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
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<0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
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pinctrl-0 = <&pcie_pins>;
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pinctrl-names = "default";
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port00: pci@0,0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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reset-gpios = <&pinctrl_ap 152 0>;
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max-link-speed = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
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<0 0 0 2 &port00 0 0 0 1>,
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<0 0 0 3 &port00 0 0 0 2>,
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<0 0 0 4 &port00 0 0 0 3>;
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};
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port01: pci@1,0 {
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device_type = "pci";
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reg = <0x800 0x0 0x0 0x0 0x0>;
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reset-gpios = <&pinctrl_ap 153 0>;
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max-link-speed = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
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<0 0 0 2 &port01 0 0 0 1>,
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<0 0 0 3 &port01 0 0 0 2>,
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<0 0 0 4 &port01 0 0 0 3>;
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};
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port02: pci@2,0 {
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device_type = "pci";
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reg = <0x1000 0x0 0x0 0x0 0x0>;
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reset-gpios = <&pinctrl_ap 33 0>;
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max-link-speed = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
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<0 0 0 2 &port02 0 0 0 1>,
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<0 0 0 3 &port02 0 0 0 2>,
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<0 0 0 4 &port02 0 0 0 3>;
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};
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};
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};
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};

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