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arm64/hwcap: Define hwcaps for 2023 DPISA features
The 2023 architecture extensions include a large number of floating point features, most of which simply add new instructions. Add hwcaps so that userspace can enumerate these features. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Catalin Marinas <[email protected]>
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‎Documentation/arch/arm64/elf_hwcaps.rst

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -317,6 +317,55 @@ HWCAP2_LRCPC3
317317
HWCAP2_LSE128
318318
Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
319319

320+
HWCAP2_FPMR
321+
Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001.
322+
323+
HWCAP2_LUT
324+
Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001.
325+
326+
HWCAP2_FAMINMAX
327+
Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001.
328+
329+
HWCAP2_F8CVT
330+
Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1.
331+
332+
HWCAP2_F8FMA
333+
Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1.
334+
335+
HWCAP2_F8DP4
336+
Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1.
337+
338+
HWCAP2_F8DP2
339+
Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1.
340+
341+
HWCAP2_F8E4M3
342+
Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1.
343+
344+
HWCAP2_F8E5M2
345+
Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1.
346+
347+
HWCAP2_SME_LUTV2
348+
Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1.
349+
350+
HWCAP2_SME_F8F16
351+
Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1.
352+
353+
HWCAP2_SME_F8F32
354+
Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1.
355+
356+
HWCAP2_SME_SF8FMA
357+
Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1.
358+
359+
HWCAP2_SME_SF8DP4
360+
Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
361+
362+
HWCAP2_SME_SF8DP2
363+
Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1.
364+
365+
HWCAP2_SME_SF8DP4
366+
Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
367+
368+
320369
4. Unused AT_HWCAP bits
321370
-----------------------
322371

‎arch/arm64/include/asm/hwcap.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,21 @@
142142
#define KERNEL_HWCAP_SVE_B16B16 __khwcap2_feature(SVE_B16B16)
143143
#define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3)
144144
#define KERNEL_HWCAP_LSE128 __khwcap2_feature(LSE128)
145+
#define KERNEL_HWCAP_FPMR __khwcap2_feature(FPMR)
146+
#define KERNEL_HWCAP_LUT __khwcap2_feature(LUT)
147+
#define KERNEL_HWCAP_FAMINMAX __khwcap2_feature(FAMINMAX)
148+
#define KERNEL_HWCAP_F8CVT __khwcap2_feature(F8CVT)
149+
#define KERNEL_HWCAP_F8FMA __khwcap2_feature(F8FMA)
150+
#define KERNEL_HWCAP_F8DP4 __khwcap2_feature(F8DP4)
151+
#define KERNEL_HWCAP_F8DP2 __khwcap2_feature(F8DP2)
152+
#define KERNEL_HWCAP_F8E4M3 __khwcap2_feature(F8E4M3)
153+
#define KERNEL_HWCAP_F8E5M2 __khwcap2_feature(F8E5M2)
154+
#define KERNEL_HWCAP_SME_LUTV2 __khwcap2_feature(SME_LUTV2)
155+
#define KERNEL_HWCAP_SME_F8F16 __khwcap2_feature(SME_F8F16)
156+
#define KERNEL_HWCAP_SME_F8F32 __khwcap2_feature(SME_F8F32)
157+
#define KERNEL_HWCAP_SME_SF8FMA __khwcap2_feature(SME_SF8FMA)
158+
#define KERNEL_HWCAP_SME_SF8DP4 __khwcap2_feature(SME_SF8DP4)
159+
#define KERNEL_HWCAP_SME_SF8DP2 __khwcap2_feature(SME_SF8DP2)
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146161
/*
147162
* This yields a mask that user programs can use to figure out what

‎arch/arm64/include/uapi/asm/hwcap.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,5 +107,20 @@
107107
#define HWCAP2_SVE_B16B16 (1UL << 45)
108108
#define HWCAP2_LRCPC3 (1UL << 46)
109109
#define HWCAP2_LSE128 (1UL << 47)
110+
#define HWCAP2_FPMR (1UL << 48)
111+
#define HWCAP2_LUT (1UL << 49)
112+
#define HWCAP2_FAMINMAX (1UL << 50)
113+
#define HWCAP2_F8CVT (1UL << 51)
114+
#define HWCAP2_F8FMA (1UL << 52)
115+
#define HWCAP2_F8DP4 (1UL << 53)
116+
#define HWCAP2_F8DP2 (1UL << 54)
117+
#define HWCAP2_F8E4M3 (1UL << 55)
118+
#define HWCAP2_F8E5M2 (1UL << 56)
119+
#define HWCAP2_SME_LUTV2 (1UL << 57)
120+
#define HWCAP2_SME_F8F16 (1UL << 58)
121+
#define HWCAP2_SME_F8F32 (1UL << 59)
122+
#define HWCAP2_SME_SF8FMA (1UL << 60)
123+
#define HWCAP2_SME_SF8DP4 (1UL << 61)
124+
#define HWCAP2_SME_SF8DP2 (1UL << 62)
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111126
#endif /* _UAPI__ASM_HWCAP_H */

‎arch/arm64/kernel/cpufeature.c

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -220,6 +220,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
220220
};
221221

222222
static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
223+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0),
223224
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
224225
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
225226
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0),
@@ -235,6 +236,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
235236
};
236237

237238
static const struct arm64_ftr_bits ftr_id_aa64isar3[] = {
239+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0),
238240
ARM64_FTR_END,
239241
};
240242

@@ -303,6 +305,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
303305
static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
304306
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
305307
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
308+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
309+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0),
306310
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
307311
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0),
308312
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
@@ -315,6 +319,10 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
315319
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0),
316320
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
317321
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0),
322+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
323+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0),
324+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
325+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0),
318326
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
319327
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
320328
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
@@ -325,10 +333,22 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
325333
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0),
326334
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
327335
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
336+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
337+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0),
338+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
339+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0),
340+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
341+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0),
328342
ARM64_FTR_END,
329343
};
330344

331345
static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = {
346+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0),
347+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0),
348+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0),
349+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0),
350+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0),
351+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0),
332352
ARM64_FTR_END,
333353
};
334354

@@ -2859,6 +2879,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
28592879
HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
28602880
HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
28612881
HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT),
2882+
HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR),
28622883
HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
28632884
HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
28642885
HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
@@ -2872,6 +2893,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
28722893
HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16),
28732894
HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH),
28742895
HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2896+
HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT),
2897+
HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX),
28752898
HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
28762899
#ifdef CONFIG_ARM64_SVE
28772900
HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
@@ -2912,19 +2935,31 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
29122935
#ifdef CONFIG_ARM64_SME
29132936
HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
29142937
HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
2938+
HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2),
29152939
HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1),
29162940
HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2),
29172941
HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
29182942
HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
29192943
HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32),
29202944
HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16),
29212945
HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16),
2946+
HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16),
2947+
HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32),
29222948
HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
29232949
HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
29242950
HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
29252951
HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
29262952
HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
2953+
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA),
2954+
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4),
2955+
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2),
29272956
#endif /* CONFIG_ARM64_SME */
2957+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT),
2958+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA),
2959+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4),
2960+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2),
2961+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3),
2962+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2),
29282963
{},
29292964
};
29302965

‎arch/arm64/kernel/cpuinfo.c

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,21 @@ static const char *const hwcap_str[] = {
128128
[KERNEL_HWCAP_SVE_B16B16] = "sveb16b16",
129129
[KERNEL_HWCAP_LRCPC3] = "lrcpc3",
130130
[KERNEL_HWCAP_LSE128] = "lse128",
131+
[KERNEL_HWCAP_FPMR] = "fpmr",
132+
[KERNEL_HWCAP_LUT] = "lut",
133+
[KERNEL_HWCAP_FAMINMAX] = "faminmax",
134+
[KERNEL_HWCAP_F8CVT] = "f8cvt",
135+
[KERNEL_HWCAP_F8FMA] = "f8fma",
136+
[KERNEL_HWCAP_F8DP4] = "f8dp4",
137+
[KERNEL_HWCAP_F8DP2] = "f8dp2",
138+
[KERNEL_HWCAP_F8E4M3] = "f8e4m3",
139+
[KERNEL_HWCAP_F8E5M2] = "f8e5m2",
140+
[KERNEL_HWCAP_SME_LUTV2] = "smelutv2",
141+
[KERNEL_HWCAP_SME_F8F16] = "smef8f16",
142+
[KERNEL_HWCAP_SME_F8F32] = "smef8f32",
143+
[KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma",
144+
[KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4",
145+
[KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2",
131146
};
132147

133148
#ifdef CONFIG_COMPAT

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