@@ -406,3 +406,38 @@ static void amdgpu_gfx_rlc_init_microcode_v2_2(struct amdgpu_device *adev)
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}
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}
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}
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+
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+ static void amdgpu_gfx_rlc_init_microcode_v2_3 (struct amdgpu_device * adev )
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+ {
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+ const struct rlc_firmware_header_v2_3 * rlc_hdr ;
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+ struct amdgpu_firmware_info * info ;
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+
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+ rlc_hdr = (const struct rlc_firmware_header_v2_3 * )adev -> gfx .rlc_fw -> data ;
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+ adev -> gfx .rlcp_ucode_version = le32_to_cpu (rlc_hdr -> rlcp_ucode_version );
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+ adev -> gfx .rlcp_ucode_feature_version = le32_to_cpu (rlc_hdr -> rlcp_ucode_feature_version );
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+ adev -> gfx .rlc .rlcp_ucode_size_bytes = le32_to_cpu (rlc_hdr -> rlcp_ucode_size_bytes );
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+ adev -> gfx .rlc .rlcp_ucode = (u8 * )rlc_hdr + le32_to_cpu (rlc_hdr -> rlcp_ucode_offset_bytes );
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+
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+ adev -> gfx .rlcv_ucode_version = le32_to_cpu (rlc_hdr -> rlcv_ucode_version );
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+ adev -> gfx .rlcv_ucode_feature_version = le32_to_cpu (rlc_hdr -> rlcv_ucode_feature_version );
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+ adev -> gfx .rlc .rlcv_ucode_size_bytes = le32_to_cpu (rlc_hdr -> rlcv_ucode_size_bytes );
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+ adev -> gfx .rlc .rlcv_ucode = (u8 * )rlc_hdr + le32_to_cpu (rlc_hdr -> rlcv_ucode_offset_bytes );
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+
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+ if (adev -> firmware .load_type == AMDGPU_FW_LOAD_PSP ) {
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+ if (adev -> gfx .rlc .rlcp_ucode_size_bytes ) {
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+ info = & adev -> firmware .ucode [AMDGPU_UCODE_ID_RLC_P ];
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+ info -> ucode_id = AMDGPU_UCODE_ID_RLC_P ;
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+ info -> fw = adev -> gfx .rlc_fw ;
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+ adev -> firmware .fw_size +=
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+ ALIGN (adev -> gfx .rlc .rlcp_ucode_size_bytes , PAGE_SIZE );
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+ }
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+
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+ if (adev -> gfx .rlc .rlcv_ucode_size_bytes ) {
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+ info = & adev -> firmware .ucode [AMDGPU_UCODE_ID_RLC_V ];
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+ info -> ucode_id = AMDGPU_UCODE_ID_RLC_V ;
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+ info -> fw = adev -> gfx .rlc_fw ;
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+ adev -> firmware .fw_size +=
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+ ALIGN (adev -> gfx .rlc .rlcv_ucode_size_bytes , PAGE_SIZE );
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+ }
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+ }
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+ }
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