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| 1 | +# SPDX-License-Identifier: GPL-2.0-only |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Marvell MMP/Orion Interrupt controller bindings |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Thomas Gleixner <[email protected]> |
| 11 | + - Jason Cooper <[email protected]> |
| 12 | + - Marc Zyngier <[email protected]> |
| 13 | + |
| 14 | + |
| 15 | +allOf: |
| 16 | + - if: |
| 17 | + properties: |
| 18 | + compatible: |
| 19 | + not: |
| 20 | + contains: |
| 21 | + const: marvell,orion-intc |
| 22 | + then: |
| 23 | + required: |
| 24 | + - mrvl,intc-nr-irqs |
| 25 | + - if: |
| 26 | + properties: |
| 27 | + compatible: |
| 28 | + contains: |
| 29 | + enum: |
| 30 | + - mrvl,mmp-intc |
| 31 | + - mrvl,mmp2-intc |
| 32 | + then: |
| 33 | + properties: |
| 34 | + reg: |
| 35 | + maxItems: 1 |
| 36 | + - if: |
| 37 | + properties: |
| 38 | + compatible: |
| 39 | + contains: |
| 40 | + enum: |
| 41 | + - marvell,mmp3-intc |
| 42 | + - mrvl,mmp2-mux-intc |
| 43 | + then: |
| 44 | + properties: |
| 45 | + reg: |
| 46 | + minItems: 2 |
| 47 | + - if: |
| 48 | + properties: |
| 49 | + compatible: |
| 50 | + contains: |
| 51 | + const: mrvl,mmp2-mux-intc |
| 52 | + then: |
| 53 | + properties: |
| 54 | + interrupts: |
| 55 | + maxItems: 1 |
| 56 | + reg-names: |
| 57 | + items: |
| 58 | + - const: 'mux status' |
| 59 | + - const: 'mux mask' |
| 60 | + required: |
| 61 | + - interrupts |
| 62 | + else: |
| 63 | + properties: |
| 64 | + interrupts: false |
| 65 | + |
| 66 | +properties: |
| 67 | + '#interrupt-cells': |
| 68 | + const: 1 |
| 69 | + |
| 70 | + compatible: |
| 71 | + enum: |
| 72 | + - mrvl,mmp-intc |
| 73 | + - mrvl,mmp2-intc |
| 74 | + - marvell,mmp3-intc |
| 75 | + - marvell,orion-intc |
| 76 | + - mrvl,mmp2-mux-intc |
| 77 | + |
| 78 | + reg: |
| 79 | + minItems: 1 |
| 80 | + maxItems: 2 |
| 81 | + |
| 82 | + reg-names: true |
| 83 | + |
| 84 | + interrupts: true |
| 85 | + |
| 86 | + interrupt-controller: true |
| 87 | + |
| 88 | + mrvl,intc-nr-irqs: |
| 89 | + description: | |
| 90 | + Specifies the number of interrupts in the interrupt controller. |
| 91 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 92 | + |
| 93 | + mrvl,clr-mfp-irq: |
| 94 | + description: | |
| 95 | + Specifies the interrupt that needs to clear MFP edge detection first. |
| 96 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 97 | + |
| 98 | +required: |
| 99 | + - '#interrupt-cells' |
| 100 | + - compatible |
| 101 | + - reg |
| 102 | + - interrupt-controller |
| 103 | + |
| 104 | +additionalProperties: false |
| 105 | + |
| 106 | +examples: |
| 107 | + - | |
| 108 | + interrupt-controller@d4282000 { |
| 109 | + compatible = "mrvl,mmp2-intc"; |
| 110 | + interrupt-controller; |
| 111 | + #interrupt-cells = <1>; |
| 112 | + reg = <0xd4282000 0x1000>; |
| 113 | + mrvl,intc-nr-irqs = <64>; |
| 114 | + }; |
| 115 | +
|
| 116 | + interrupt-controller@d4282150 { |
| 117 | + compatible = "mrvl,mmp2-mux-intc"; |
| 118 | + interrupts = <4>; |
| 119 | + interrupt-controller; |
| 120 | + #interrupt-cells = <1>; |
| 121 | + reg = <0x150 0x4>, <0x168 0x4>; |
| 122 | + reg-names = "mux status", "mux mask"; |
| 123 | + mrvl,intc-nr-irqs = <2>; |
| 124 | + }; |
| 125 | + - | |
| 126 | + interrupt-controller@fed20204 { |
| 127 | + compatible = "marvell,orion-intc"; |
| 128 | + interrupt-controller; |
| 129 | + #interrupt-cells = <1>; |
| 130 | + reg = <0xfed20204 0x04>, |
| 131 | + <0xfed20214 0x04>; |
| 132 | + }; |
| 133 | +
|
| 134 | +... |
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