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James-A-ClarkMarc Zyngier
James-A-Clark
authored and
Marc Zyngier
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arm64/sysreg/tools: Move TRFCR definitions to sysreg
Convert TRFCR to automatic generation. Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous definition so no code change is required. Also add TRFCR_EL12 which will start to be used in a later commit. Unfortunately, to avoid breaking the Perf build with duplicate definition errors, the tools copy of the sysreg.h header needs to be updated at the same time rather than the usual second commit. This is because the generated version of sysreg (arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared and tools/ does not have its own copy. Reviewed-by: Mark Brown <[email protected]> Signed-off-by: James Clark <[email protected]> Signed-off-by: James Clark <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marc Zyngier <[email protected]>
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‎arch/arm64/include/asm/sysreg.h

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -283,8 +283,6 @@
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#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
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#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
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286-
#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
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#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
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#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
@@ -519,7 +517,6 @@
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#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
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#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
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522-
#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
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#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
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#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
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#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
@@ -983,15 +980,6 @@
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/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
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#define SYS_MPIDR_SAFE_VAL (BIT(31))
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986-
#define TRFCR_ELx_TS_SHIFT 5
987-
#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
988-
#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
989-
#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
990-
#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
991-
#define TRFCR_EL2_CX BIT(3)
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#define TRFCR_ELx_ExTRE BIT(1)
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#define TRFCR_ELx_E0TRE BIT(0)
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/* GIC Hypervisor interface registers */
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/* ICH_MISR_EL2 bit definitions */
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#define ICH_MISR_EOI (1 << 0)

‎arch/arm64/tools/sysreg

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1995,6 +1995,22 @@ Sysreg CPACR_EL1 3 0 1 0 2
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Fields CPACR_ELx
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EndSysreg
19971997

1998+
SysregFields TRFCR_ELx
1999+
Res0 63:7
2000+
UnsignedEnum 6:5 TS
2001+
0b0001 VIRTUAL
2002+
0b0010 GUEST_PHYSICAL
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0b0011 PHYSICAL
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EndEnum
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Res0 4:2
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Field 1 ExTRE
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Field 0 E0TRE
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EndSysregFields
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2010+
Sysreg TRFCR_EL1 3 0 1 2 1
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Fields TRFCR_ELx
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EndSysreg
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Sysreg SMPRI_EL1 3 0 1 2 4
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Res0 63:4
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Field 3:0 PRIORITY
@@ -2544,6 +2560,22 @@ Field 1 ICIALLU
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Field 0 ICIALLUIS
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EndSysreg
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Sysreg TRFCR_EL2 3 4 1 2 1
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Res0 63:7
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UnsignedEnum 6:5 TS
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0b0000 USE_TRFCR_EL1_TS
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0b0001 VIRTUAL
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0b0010 GUEST_PHYSICAL
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0b0011 PHYSICAL
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EndEnum
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Res0 4
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Field 3 CX
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Res0 2
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Field 1 E2TRE
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Field 0 E0HTRE
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EndSysreg
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Sysreg HDFGRTR_EL2 3 4 3 1 4
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Field 63 PMBIDR_EL1
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Field 62 nPMSNEVFR_EL1
@@ -2954,6 +2986,10 @@ Sysreg ZCR_EL12 3 5 1 2 0
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Fields ZCR_ELx
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EndSysreg
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2989+
Sysreg TRFCR_EL12 3 5 1 2 1
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Fields TRFCR_ELx
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EndSysreg
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Sysreg SMCR_EL12 3 5 1 2 6
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Fields SMCR_ELx
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EndSysreg

‎tools/arch/arm64/include/asm/sysreg.h

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -283,8 +283,6 @@
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#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
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#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
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286-
#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
287-
288286
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
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290288
#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
@@ -519,7 +517,6 @@
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#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
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#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
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522-
#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
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#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
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#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
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#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
@@ -983,15 +980,6 @@
983980
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
984981
#define SYS_MPIDR_SAFE_VAL (BIT(31))
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986-
#define TRFCR_ELx_TS_SHIFT 5
987-
#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
988-
#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
989-
#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
990-
#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
991-
#define TRFCR_EL2_CX BIT(3)
992-
#define TRFCR_ELx_ExTRE BIT(1)
993-
#define TRFCR_ELx_E0TRE BIT(0)
994-
995983
/* GIC Hypervisor interface registers */
996984
/* ICH_MISR_EL2 bit definitions */
997985
#define ICH_MISR_EOI (1 << 0)

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