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*/
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#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
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- #define SPI_NOR_MAX_ADDR_WIDTH 4
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+ #define SPI_NOR_MAX_ADDR_NBYTES 4
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#define SPI_NOR_SRST_SLEEP_MIN 200
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#define SPI_NOR_SRST_SLEEP_MAX 400
@@ -198,7 +198,7 @@ static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
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{
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struct spi_mem_op op =
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SPI_MEM_OP (SPI_MEM_OP_CMD (nor -> read_opcode , 0 ),
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- SPI_MEM_OP_ADDR (nor -> addr_width , from , 0 ),
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+ SPI_MEM_OP_ADDR (nor -> addr_nbytes , from , 0 ),
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SPI_MEM_OP_DUMMY (nor -> read_dummy , 0 ),
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SPI_MEM_OP_DATA_IN (len , buf , 0 ));
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bool usebouncebuf ;
@@ -262,7 +262,7 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
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{
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struct spi_mem_op op =
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SPI_MEM_OP (SPI_MEM_OP_CMD (nor -> program_opcode , 0 ),
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- SPI_MEM_OP_ADDR (nor -> addr_width , to , 0 ),
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+ SPI_MEM_OP_ADDR (nor -> addr_nbytes , to , 0 ),
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SPI_MEM_OP_NO_DUMMY ,
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SPI_MEM_OP_DATA_OUT (len , buf , 0 ));
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ssize_t nbytes ;
@@ -1113,7 +1113,7 @@ int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
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if (nor -> spimem ) {
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struct spi_mem_op op =
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SPI_NOR_SECTOR_ERASE_OP (nor -> erase_opcode ,
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- nor -> addr_width , addr );
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+ nor -> addr_nbytes , addr );
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spi_nor_spimem_setup_op (nor , & op , nor -> write_proto );
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@@ -1126,13 +1126,13 @@ int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
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* Default implementation, if driver doesn't have a specialized HW
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* control
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*/
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- for (i = nor -> addr_width - 1 ; i >= 0 ; i -- ) {
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+ for (i = nor -> addr_nbytes - 1 ; i >= 0 ; i -- ) {
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nor -> bouncebuf [i ] = addr & 0xff ;
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addr >>= 8 ;
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}
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return spi_nor_controller_ops_write_reg (nor , nor -> erase_opcode ,
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- nor -> bouncebuf , nor -> addr_width );
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+ nor -> bouncebuf , nor -> addr_nbytes );
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}
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/**
@@ -2249,43 +2249,43 @@ static int spi_nor_default_setup(struct spi_nor *nor,
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return 0 ;
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}
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- static int spi_nor_set_addr_width (struct spi_nor * nor )
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+ static int spi_nor_set_addr_nbytes (struct spi_nor * nor )
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{
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- if (nor -> addr_width ) {
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+ if (nor -> addr_nbytes ) {
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/* already configured from SFDP */
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} else if (nor -> read_proto == SNOR_PROTO_8_8_8_DTR ) {
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/*
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* In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
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- * in this protocol an odd address width cannot be used because
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+ * in this protocol an odd addr_nbytes cannot be used because
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* then the address phase would only span a cycle and a half.
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* Half a cycle would be left over. We would then have to start
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* the dummy phase in the middle of a cycle and so too the data
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* phase, and we will end the transaction with half a cycle left
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* over.
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*
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- * Force all 8D-8D-8D flashes to use an address width of 4 to
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+ * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to
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* avoid this situation.
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*/
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- nor -> addr_width = 4 ;
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- } else if (nor -> info -> addr_width ) {
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- nor -> addr_width = nor -> info -> addr_width ;
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+ nor -> addr_nbytes = 4 ;
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+ } else if (nor -> info -> addr_nbytes ) {
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+ nor -> addr_nbytes = nor -> info -> addr_nbytes ;
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} else {
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- nor -> addr_width = 3 ;
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+ nor -> addr_nbytes = 3 ;
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}
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- if (nor -> addr_width == 3 && nor -> params -> size > 0x1000000 ) {
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+ if (nor -> addr_nbytes == 3 && nor -> params -> size > 0x1000000 ) {
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/* enable 4-byte addressing if the device exceeds 16MiB */
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- nor -> addr_width = 4 ;
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+ nor -> addr_nbytes = 4 ;
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}
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- if (nor -> addr_width > SPI_NOR_MAX_ADDR_WIDTH ) {
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- dev_dbg (nor -> dev , "address width is too large: %u\n" ,
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- nor -> addr_width );
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+ if (nor -> addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES ) {
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+ dev_dbg (nor -> dev , "The number of address bytes is too large: %u\n" ,
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+ nor -> addr_nbytes );
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return - EINVAL ;
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}
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/* Set 4byte opcodes when possible. */
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- if (nor -> addr_width == 4 && nor -> flags & SNOR_F_4B_OPCODES &&
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+ if (nor -> addr_nbytes == 4 && nor -> flags & SNOR_F_4B_OPCODES &&
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!(nor -> flags & SNOR_F_HAS_4BAIT ))
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spi_nor_set_4byte_opcodes (nor );
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@@ -2304,7 +2304,7 @@ static int spi_nor_setup(struct spi_nor *nor,
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if (ret )
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return ret ;
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- return spi_nor_set_addr_width (nor );
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+ return spi_nor_set_addr_nbytes (nor );
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}
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/**
@@ -2492,7 +2492,7 @@ static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)
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if (spi_nor_parse_sfdp (nor )) {
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memcpy (nor -> params , & sfdp_params , sizeof (* nor -> params ));
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- nor -> addr_width = 0 ;
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+ nor -> addr_nbytes = 0 ;
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nor -> flags &= ~SNOR_F_4B_OPCODES ;
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}
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}
@@ -2713,7 +2713,7 @@ static int spi_nor_init(struct spi_nor *nor)
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nor -> flags & SNOR_F_SWP_IS_VOLATILE ))
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spi_nor_try_unlock_all (nor );
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- if (nor -> addr_width == 4 &&
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+ if (nor -> addr_nbytes == 4 &&
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nor -> read_proto != SNOR_PROTO_8_8_8_DTR &&
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!(nor -> flags & SNOR_F_4B_OPCODES )) {
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/*
@@ -2840,7 +2840,7 @@ static void spi_nor_put_device(struct mtd_info *mtd)
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void spi_nor_restore (struct spi_nor * nor )
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{
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/* restore the addressing mode */
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- if (nor -> addr_width == 4 && !(nor -> flags & SNOR_F_4B_OPCODES ) &&
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+ if (nor -> addr_nbytes == 4 && !(nor -> flags & SNOR_F_4B_OPCODES ) &&
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nor -> flags & SNOR_F_BROKEN_RESET )
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nor -> params -> set_4byte_addr_mode (nor , false);
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@@ -2984,7 +2984,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
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* - select op codes for (Fast) Read, Page Program and Sector Erase.
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* - set the number of dummy cycles (mode cycles + wait states).
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* - set the SPI protocols for register and memory accesses.
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- * - set the address width .
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+ * - set the number of address bytes .
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*/
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ret = spi_nor_setup (nor , hwcaps );
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if (ret )
@@ -3025,7 +3025,7 @@ static int spi_nor_create_read_dirmap(struct spi_nor *nor)
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{
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struct spi_mem_dirmap_info info = {
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.op_tmpl = SPI_MEM_OP (SPI_MEM_OP_CMD (nor -> read_opcode , 0 ),
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- SPI_MEM_OP_ADDR (nor -> addr_width , 0 , 0 ),
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+ SPI_MEM_OP_ADDR (nor -> addr_nbytes , 0 , 0 ),
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SPI_MEM_OP_DUMMY (nor -> read_dummy , 0 ),
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SPI_MEM_OP_DATA_IN (0 , NULL , 0 )),
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.offset = 0 ,
@@ -3056,7 +3056,7 @@ static int spi_nor_create_write_dirmap(struct spi_nor *nor)
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{
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struct spi_mem_dirmap_info info = {
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.op_tmpl = SPI_MEM_OP (SPI_MEM_OP_CMD (nor -> program_opcode , 0 ),
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- SPI_MEM_OP_ADDR (nor -> addr_width , 0 , 0 ),
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+ SPI_MEM_OP_ADDR (nor -> addr_nbytes , 0 , 0 ),
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SPI_MEM_OP_NO_DUMMY ,
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SPI_MEM_OP_DATA_OUT (0 , NULL , 0 )),
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.offset = 0 ,
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