Skip to content

Commit c46104f

Browse files
bebarinobebarino
committed
Merge tag 'renesas-clk-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs * tag 'renesas-clk-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1 clk: renesas: rzg2l: Check reset monitor registers clk: renesas: r9a08g045: Add IA55 pclk and its reset
2 parents be587cb + 515f05d commit c46104f

File tree

2 files changed

+57
-15
lines changed

2 files changed

+57
-15
lines changed

‎drivers/clk/renesas/r9a08g045-cpg.c

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -181,13 +181,16 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
181181
DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS,
182182
dtable_1_32, 0, 0, 0, NULL),
183183
DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2),
184+
DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1),
184185
DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2),
185186
DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
186187
DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),
188+
DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2),
187189
};
188190

189191
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
190192
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
193+
DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
191194
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
192195
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
193196
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
@@ -202,16 +205,25 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
202205
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
203206
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
204207
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
208+
DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0),
209+
DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0),
210+
DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8),
211+
DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
212+
DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
213+
DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
205214
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
206215
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
207216
};
208217

209218
static const struct rzg2l_reset r9a08g045_resets[] = {
210219
DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
211220
DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
221+
DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
212222
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
213223
DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
214224
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
225+
DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
226+
DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
215227
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
216228
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
217229
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
@@ -220,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
220232

221233
static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
222234
MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
235+
MOD_CLK_BASE + R9A08G045_IA55_PCLK,
223236
MOD_CLK_BASE + R9A08G045_IA55_CLK,
224237
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
225238
};

‎drivers/clk/renesas/rzg2l-cpg.c

Lines changed: 44 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1416,12 +1416,27 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
14161416
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
14171417
const struct rzg2l_cpg_info *info = priv->info;
14181418
unsigned int reg = info->resets[id].off;
1419-
u32 value = BIT(info->resets[id].bit) << 16;
1419+
u32 mask = BIT(info->resets[id].bit);
1420+
s8 monbit = info->resets[id].monbit;
1421+
u32 value = mask << 16;
14201422

14211423
dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
14221424

14231425
writel(value, priv->base + CLK_RST_R(reg));
1424-
return 0;
1426+
1427+
if (info->has_clk_mon_regs) {
1428+
reg = CLK_MRST_R(reg);
1429+
} else if (monbit >= 0) {
1430+
reg = CPG_RST_MON;
1431+
mask = BIT(monbit);
1432+
} else {
1433+
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
1434+
udelay(35);
1435+
return 0;
1436+
}
1437+
1438+
return readl_poll_timeout_atomic(priv->base + reg, value,
1439+
value & mask, 10, 200);
14251440
}
14261441

14271442
static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
@@ -1430,14 +1445,28 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
14301445
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
14311446
const struct rzg2l_cpg_info *info = priv->info;
14321447
unsigned int reg = info->resets[id].off;
1433-
u32 dis = BIT(info->resets[id].bit);
1434-
u32 value = (dis << 16) | dis;
1448+
u32 mask = BIT(info->resets[id].bit);
1449+
s8 monbit = info->resets[id].monbit;
1450+
u32 value = (mask << 16) | mask;
14351451

14361452
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
14371453
CLK_RST_R(reg));
14381454

14391455
writel(value, priv->base + CLK_RST_R(reg));
1440-
return 0;
1456+
1457+
if (info->has_clk_mon_regs) {
1458+
reg = CLK_MRST_R(reg);
1459+
} else if (monbit >= 0) {
1460+
reg = CPG_RST_MON;
1461+
mask = BIT(monbit);
1462+
} else {
1463+
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
1464+
udelay(35);
1465+
return 0;
1466+
}
1467+
1468+
return readl_poll_timeout_atomic(priv->base + reg, value,
1469+
!(value & mask), 10, 200);
14411470
}
14421471

14431472
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
@@ -1449,9 +1478,6 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
14491478
if (ret)
14501479
return ret;
14511480

1452-
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
1453-
udelay(35);
1454-
14551481
return rzg2l_cpg_deassert(rcdev, id);
14561482
}
14571483

@@ -1460,18 +1486,21 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
14601486
{
14611487
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
14621488
const struct rzg2l_cpg_info *info = priv->info;
1463-
unsigned int reg = info->resets[id].off;
1464-
u32 bitmask = BIT(info->resets[id].bit);
14651489
s8 monbit = info->resets[id].monbit;
1490+
unsigned int reg;
1491+
u32 bitmask;
14661492

14671493
if (info->has_clk_mon_regs) {
1468-
return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
1494+
reg = CLK_MRST_R(info->resets[id].off);
1495+
bitmask = BIT(info->resets[id].bit);
14691496
} else if (monbit >= 0) {
1470-
u32 monbitmask = BIT(monbit);
1471-
1472-
return !!(readl(priv->base + CPG_RST_MON) & monbitmask);
1497+
reg = CPG_RST_MON;
1498+
bitmask = BIT(monbit);
1499+
} else {
1500+
return -ENOTSUPP;
14731501
}
1474-
return -ENOTSUPP;
1502+
1503+
return !!(readl(priv->base + reg) & bitmask);
14751504
}
14761505

14771506
static const struct reset_control_ops rzg2l_cpg_reset_ops = {

0 commit comments

Comments
 (0)