PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling

PCIe CEM r5.1, sec 2.9.2, mandates that the PERST# signal must remain
asserted for at least 100 usec (Tperst-clk) after the PCIe reference clock
becomes stable (if a reference clock is supplied), and for at least 100
msec after the power is stable (Tpvperl, defined by the macro
PCIE_T_PVPERL_MS).

Modify rockchip_pcie_host_init_port() to satisfy these constraints by
adding a sleep period before deasserting PERST# using the ep_gpio GPIO.
Since Tperst-clk is the shorter wait time, add an msleep() call for the
longer PCIE_T_PVPERL_MS milliseconds to handle both timing requirements.

Link: https://lore.kernel.org/linux-pci/[email protected]
Signed-off-by: Damien Le Moal <[email protected]>
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>

Author: damien-lemoal

drivers/pci/controller/pcie-rockchip-host.c

@@ -322,6 +322,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
 	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
 			    PCIE_CLIENT_CONFIG);
 
+	msleep(PCIE_T_PVPERL_MS);
 	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
 
 	/* 500ms timeout value should be enough for Gen1/2 training */