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#define WAIT_RETRIES 5
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#define RX_BUSY 0
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+ #define RX_BURST_LEVEL 16
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#define TX_BUSY 1
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+ #define TX_BURST_LEVEL 16
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static bool mid_spi_dma_chan_filter (struct dma_chan * chan , void * param )
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{
@@ -227,7 +229,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
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memset (& txconf , 0 , sizeof (txconf ));
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txconf .direction = DMA_MEM_TO_DEV ;
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txconf .dst_addr = dws -> dma_addr ;
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- txconf .dst_maxburst = 16 ;
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+ txconf .dst_maxburst = TX_BURST_LEVEL ;
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txconf .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES ;
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txconf .dst_addr_width = convert_dma_width (dws -> n_bytes );
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txconf .device_fc = false;
@@ -319,7 +321,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
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memset (& rxconf , 0 , sizeof (rxconf ));
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rxconf .direction = DMA_DEV_TO_MEM ;
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rxconf .src_addr = dws -> dma_addr ;
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- rxconf .src_maxburst = 16 ;
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+ rxconf .src_maxburst = RX_BURST_LEVEL ;
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rxconf .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES ;
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rxconf .src_addr_width = convert_dma_width (dws -> n_bytes );
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rxconf .device_fc = false;
@@ -344,8 +346,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
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{
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u16 imr = 0 , dma_ctrl = 0 ;
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- dw_writel (dws , DW_SPI_DMARDLR , 0xf );
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- dw_writel (dws , DW_SPI_DMATDLR , 0x10 );
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+ dw_writel (dws , DW_SPI_DMARDLR , RX_BURST_LEVEL - 1 );
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+ dw_writel (dws , DW_SPI_DMATDLR , TX_BURST_LEVEL );
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if (xfer -> tx_buf ) {
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dma_ctrl |= SPI_DMA_TDMAE ;
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