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tlebkwilczynski
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PCI: j721e: Add suspend and resume support
Add suspend and resume support. Only the Root Complex mode is supported. During the suspend stage PERST# is asserted, then deasserted during the resume stage. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Théo Lebrun <[email protected]> Signed-off-by: Thomas Richard <[email protected]> [kwilczynski: commit log, update references to the PCI SIG specification] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]>
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drivers/pci/controller/cadence/pci-j721e.c

Lines changed: 92 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/container_of.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/io.h>
@@ -22,6 +24,8 @@
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#include "../../pci.h"
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#include "pcie-cadence.h"
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#define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
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#define ENABLE_REG_SYS_2 0x108
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#define STATUS_REG_SYS_2 0x508
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#define STATUS_CLR_REG_SYS_2 0x708
@@ -568,12 +572,12 @@ static int j721e_pcie_probe(struct platform_device *pdev)
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pcie->refclk = clk;
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/*
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* "Power Sequencing and Reset Signal Timings" table in
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* PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
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* indicates PERST# should be deasserted after minimum of 100us
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* once REFCLK is stable. The REFCLK to the connector in RC
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* mode is selected while enabling the PHY. So deassert PERST#
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* after 100 us.
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* The "Power Sequencing and Reset Signal Timings" table of the
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* PCI Express Card Electromechanical Specification, Revision
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* 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#
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* should be deasserted after minimum of 100us once REFCLK is
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* stable. The REFCLK to the connector in RC mode is selected
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* while enabling the PHY. So deassert PERST# after 100 us.
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*/
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if (gpiod) {
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fsleep(PCIE_T_PERST_CLK_US);
@@ -625,13 +629,95 @@ static void j721e_pcie_remove(struct platform_device *pdev)
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pm_runtime_disable(dev);
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}
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static int j721e_pcie_suspend_noirq(struct device *dev)
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{
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struct j721e_pcie *pcie = dev_get_drvdata(dev);
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if (pcie->mode == PCI_MODE_RC) {
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gpiod_set_value_cansleep(pcie->reset_gpio, 0);
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clk_disable_unprepare(pcie->refclk);
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}
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cdns_pcie_disable_phy(pcie->cdns_pcie);
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return 0;
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}
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static int j721e_pcie_resume_noirq(struct device *dev)
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{
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struct j721e_pcie *pcie = dev_get_drvdata(dev);
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struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
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int ret;
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ret = j721e_pcie_ctrl_init(pcie);
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if (ret < 0)
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return ret;
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j721e_pcie_config_link_irq(pcie);
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/*
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* This is not called explicitly in the probe, it is called by
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* cdns_pcie_init_phy().
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*/
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ret = cdns_pcie_enable_phy(pcie->cdns_pcie);
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if (ret < 0)
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return ret;
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if (pcie->mode == PCI_MODE_RC) {
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struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie);
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669+
ret = clk_prepare_enable(pcie->refclk);
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if (ret < 0)
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return ret;
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/*
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* The "Power Sequencing and Reset Signal Timings" table of the
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* PCI Express Card Electromechanical Specification, Revision
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* 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#
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* should be deasserted after minimum of 100us once REFCLK is
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* stable. The REFCLK to the connector in RC mode is selected
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* while enabling the PHY. So deassert PERST# after 100 us.
680+
*/
681+
if (pcie->reset_gpio) {
682+
fsleep(PCIE_T_PERST_CLK_US);
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gpiod_set_value_cansleep(pcie->reset_gpio, 1);
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}
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686+
ret = cdns_pcie_host_link_setup(rc);
687+
if (ret < 0) {
688+
clk_disable_unprepare(pcie->refclk);
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return ret;
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}
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/*
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* Reset internal status of BARs to force reinitialization in
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* cdns_pcie_host_init().
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*/
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for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
697+
rc->avail_ib_bar[bar] = true;
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699+
ret = cdns_pcie_host_init(rc);
700+
if (ret) {
701+
clk_disable_unprepare(pcie->refclk);
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return ret;
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}
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}
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return 0;
707+
}
708+
709+
static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops,
710+
j721e_pcie_suspend_noirq,
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j721e_pcie_resume_noirq);
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628713
static struct platform_driver j721e_pcie_driver = {
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.probe = j721e_pcie_probe,
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.remove_new = j721e_pcie_remove,
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.driver = {
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.name = "j721e-pcie",
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.of_match_table = of_j721e_pcie_match,
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.suppress_bind_attrs = true,
720+
.pm = pm_sleep_ptr(&j721e_pcie_pm_ops),
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},
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};
637723
builtin_platform_driver(j721e_pcie_driver);

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