@@ -71,10 +71,12 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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#define KVASER_PCIEFD_SYSID_BUILD_REG (KVASER_PCIEFD_SYSID_BASE + 0x14)
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/* Shared receive buffer registers */
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#define KVASER_PCIEFD_SRB_BASE 0x1f200
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+ #define KVASER_PCIEFD_SRB_FIFO_LAST_REG (KVASER_PCIEFD_SRB_BASE + 0x1f4)
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#define KVASER_PCIEFD_SRB_CMD_REG (KVASER_PCIEFD_SRB_BASE + 0x200)
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#define KVASER_PCIEFD_SRB_IEN_REG (KVASER_PCIEFD_SRB_BASE + 0x204)
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#define KVASER_PCIEFD_SRB_IRQ_REG (KVASER_PCIEFD_SRB_BASE + 0x20c)
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#define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210)
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+ #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG (KVASER_PCIEFD_SRB_BASE + 0x214)
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#define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218)
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/* EPCS flash controller registers */
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#define KVASER_PCIEFD_SPI_BASE 0x1fc00
@@ -111,6 +113,9 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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/* DMA support */
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#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
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+ /* SRB current packet level */
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+ #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK 0xff
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+
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/* DMA Enable */
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#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
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@@ -1061,6 +1066,7 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
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{
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int i ;
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u32 srb_status ;
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+ u32 srb_packet_count ;
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dma_addr_t dma_addr [KVASER_PCIEFD_DMA_COUNT ];
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/* Disable the DMA */
@@ -1088,6 +1094,15 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
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KVASER_PCIEFD_SRB_CMD_RDB1 ,
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pcie -> reg_base + KVASER_PCIEFD_SRB_CMD_REG );
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+ /* Empty Rx FIFO */
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+ srb_packet_count = ioread32 (pcie -> reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG ) &
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+ KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK ;
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+ while (srb_packet_count ) {
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+ /* Drop current packet in FIFO */
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+ ioread32 (pcie -> reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG );
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+ srb_packet_count -- ;
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+ }
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+
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srb_status = ioread32 (pcie -> reg_base + KVASER_PCIEFD_SRB_STAT_REG );
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if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI )) {
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dev_err (& pcie -> pci -> dev , "DMA not idle before enabling\n" );
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