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Merge tag 'amd-drm-fixes-5.7-2020-05-06' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
amd-drm-fixes-5.7-2020-05-06: amdgpu: - Runtime PM fixes - DC fix for PPC - Misc DC fixes Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 0e698df + e6142dd commit c61b0b9

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6 files changed

+43
-27
lines changed

6 files changed

+43
-27
lines changed

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3372,15 +3372,12 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
33723372
}
33733373
}
33743374

3375-
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3376-
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3377-
3378-
amdgpu_amdkfd_suspend(adev, !fbcon);
3379-
33803375
amdgpu_ras_suspend(adev);
33813376

33823377
r = amdgpu_device_ip_suspend_phase1(adev);
33833378

3379+
amdgpu_amdkfd_suspend(adev, !fbcon);
3380+
33843381
/* evict vram memory */
33853382
amdgpu_bo_evict_vram(adev);
33863383

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2008,17 +2008,22 @@ void amdgpu_dm_update_connector_after_detect(
20082008
dc_sink_retain(aconnector->dc_sink);
20092009
if (sink->dc_edid.length == 0) {
20102010
aconnector->edid = NULL;
2011-
drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
2011+
if (aconnector->dc_link->aux_mode) {
2012+
drm_dp_cec_unset_edid(
2013+
&aconnector->dm_dp_aux.aux);
2014+
}
20122015
} else {
20132016
aconnector->edid =
2014-
(struct edid *) sink->dc_edid.raw_edid;
2015-
2017+
(struct edid *)sink->dc_edid.raw_edid;
20162018

20172019
drm_connector_update_edid_property(connector,
2018-
aconnector->edid);
2019-
drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
2020-
aconnector->edid);
2020+
aconnector->edid);
2021+
2022+
if (aconnector->dc_link->aux_mode)
2023+
drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
2024+
aconnector->edid);
20212025
}
2026+
20222027
amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
20232028
update_connector_ext_caps(aconnector);
20242029
} else {

drivers/gpu/drm/amd/display/dc/core/dc.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -834,11 +834,10 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
834834
static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
835835
{
836836
int i;
837-
int count = 0;
838-
struct pipe_ctx *pipe;
839837
PERF_TRACE();
840838
for (i = 0; i < MAX_PIPES; i++) {
841-
pipe = &context->res_ctx.pipe_ctx[i];
839+
int count = 0;
840+
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
842841

843842
if (!pipe->plane_state)
844843
continue;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

Lines changed: 23 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3068,25 +3068,32 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
30683068
return out;
30693069
}
30703070

3071-
3072-
bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3073-
bool fast_validate)
3071+
/*
3072+
* This must be noinline to ensure anything that deals with FP registers
3073+
* is contained within this call; previously our compiling with hard-float
3074+
* would result in fp instructions being emitted outside of the boundaries
3075+
* of the DC_FP_START/END macros, which makes sense as the compiler has no
3076+
* idea about what is wrapped and what is not
3077+
*
3078+
* This is largely just a workaround to avoid breakage introduced with 5.6,
3079+
* ideally all fp-using code should be moved into its own file, only that
3080+
* should be compiled with hard-float, and all code exported from there
3081+
* should be strictly wrapped with DC_FP_START/END
3082+
*/
3083+
static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
3084+
struct dc_state *context, bool fast_validate)
30743085
{
30753086
bool voltage_supported = false;
30763087
bool full_pstate_supported = false;
30773088
bool dummy_pstate_supported = false;
30783089
double p_state_latency_us;
30793090

3080-
DC_FP_START();
30813091
p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
30823092
context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
30833093
dc->debug.disable_dram_clock_change_vactive_support;
30843094

30853095
if (fast_validate) {
3086-
voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);
3087-
3088-
DC_FP_END();
3089-
return voltage_supported;
3096+
return dcn20_validate_bandwidth_internal(dc, context, true);
30903097
}
30913098

30923099
// Best case, we support full UCLK switch latency
@@ -3115,7 +3122,15 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
31153122

31163123
restore_dml_state:
31173124
context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
3125+
return voltage_supported;
3126+
}
31183127

3128+
bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3129+
bool fast_validate)
3130+
{
3131+
bool voltage_supported = false;
3132+
DC_FP_START();
3133+
voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
31193134
DC_FP_END();
31203135
return voltage_supported;
31213136
}

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1200,7 +1200,7 @@ static void dml_rq_dlg_get_dlg_params(
12001200
min_hratio_fact_l = 1.0;
12011201
min_hratio_fact_c = 1.0;
12021202

1203-
if (htaps_l <= 1)
1203+
if (hratio_l <= 1)
12041204
min_hratio_fact_l = 2.0;
12051205
else if (htaps_l <= 6) {
12061206
if ((hratio_l * 2.0) > 4.0)
@@ -1216,7 +1216,7 @@ static void dml_rq_dlg_get_dlg_params(
12161216

12171217
hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
12181218

1219-
if (htaps_c <= 1)
1219+
if (hratio_c <= 1)
12201220
min_hratio_fact_c = 2.0;
12211221
else if (htaps_c <= 6) {
12221222
if ((hratio_c * 2.0) > 4.0)
@@ -1522,8 +1522,8 @@ static void dml_rq_dlg_get_dlg_params(
15221522

15231523
disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
15241524
disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
1525-
disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
1526-
disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
1525+
disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);
1526+
disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);
15271527

15281528
// Clamp to max for now
15291529
if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/os_types.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@
108108
#define ASSERT(expr) ASSERT_CRITICAL(expr)
109109

110110
#else
111-
#define ASSERT(expr) WARN_ON(!(expr))
111+
#define ASSERT(expr) WARN_ON_ONCE(!(expr))
112112
#endif
113113

114114
#define BREAK_TO_DEBUGGER() ASSERT(0)

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