platform/x86: p2sb: Cache correct PCI bar for P2SB on Gemini Lake

Gemini Lake (Goldmont Plus) is an Apollo Lake (Goldmont) derived design and
as such has the P2SB at device.function 13.0, rather then at the default
31.1, just like Apollo Lake.

At a mapping to P2SB_DEVFN_GOLDMONT to p2sb_cpu_ids[] for Goldmont Plus,
so that the correct PCI bar gets cached.

This fixes P2SB unhiding not working on these devices, which fixes
SPI support for the bootrom SPI controller not working.

Fixes: 2841631 ("platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe")
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Ilpo Järvinen <[email protected]>
Signed-off-by: Ilpo Järvinen <[email protected]>

Author: jwrdegoede

drivers/platform/x86/p2sb.c

@@ -25,6 +25,7 @@
 
 static const struct x86_cpu_id p2sb_cpu_ids[] = {
 	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT),
+	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, P2SB_DEVFN_GOLDMONT),
 	{}
 };