Skip to content

Commit c6f2f3e

Browse files
torvaldstorvalds
committed
Merge tag 'loongarch-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pull initial Loongarch architecture code from Arnd Bergmann: "This is the majority of the loongarch architecture code, including the final system call interface and all core functionality. It still misses three sets of peripheral but vital patches to add support for other subsystems, which have yet to pass review: - The drivers/firmware/efi stub for booting from a standard UEFI firmware implementation. Both the original custom boot interface and a draft implementation of the EFI stub did not make it, so it is currently impossible to boot the kernel, until the loongarch specific portions get accepted into the UEFI subsystem - The drivers/irqchip/irq-loongson-*.c drivers are shared with the the MIPS port, but currently lack support for ACPI based booting, which will get merged through the irqchip subsystem. - Similarly, the drivers/pci/controller/pci-loongson.c needs to be modified for ACPI support, which will be merged through the PCI subsystem. While the port cannot actually be used before all the above are merged, having it in 5.19 helps to establish the user space ABI for the libc ports to build on, and to help any treewide changes in the mainline kernel get applied here as well. A gcc-12 based tool chains for build testing is now included in https://mirrors.edge.kernel.org/pub/tools/crosstool/" Original description from Huacai Chen: "LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its boot protocol LoongArch-specific interrupt controllers (similar to APIC) are already added in the next revision of ACPI Specification (current revision is 6.4). This patchset is adding basic LoongArch support in mainline kernel, we can see a complete snapshot here: https://github.com/loongson/linux/tree/loongarch-next https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git/log/?h=loongarch-next Cross-compile tool chain to build kernel: https://github.com/loongson/build-tools/releases/download/2021.12.21/loongarch64-clfs-2022-03-03-cross-tools-gcc-glibc.tar.xz A CLFS-based Linux distro: https://github.com/loongson/build-tools/releases/download/2021.12.21/loongarch64-clfs-system-2022-03-03.tar.bz2 Open-source tool chain which is under review (Binutils and Gcc are already upstream): https://github.com/loongson/binutils-gdb/tree/upstream_v3.1 https://github.com/loongson/gcc/tree/loongarch_upstream_v6.3 https://github.com/loongson/glibc/tree/loongarch_2_35_dev_v2.2 Loongson and LoongArch documentations: https://github.com/loongson/LoongArch-Documentation LoongArch-specific interrupt controllers: https://mantis.uefi.org/mantis/view.php?id=2203 https://mantis.uefi.org/mantis/view.php?id=2313" Link: https://lore.kernel.org/lkml/[email protected]/ * tag 'loongarch-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (24 commits) MAINTAINERS: Add maintainer information for LoongArch LoongArch: Add Loongson-3 default config file LoongArch: Add Non-Uniform Memory Access (NUMA) support LoongArch: Add multi-processor (SMP) support LoongArch: Add VDSO and VSYSCALL support LoongArch: Add some library functions LoongArch: Add misc common routines LoongArch: Add ELF and module support LoongArch: Add signal handling support LoongArch: Add system call support LoongArch: Add memory management LoongArch: Add process management LoongArch: Add exception/interrupt handling LoongArch: Add boot and setup routines LoongArch: Add other common headers LoongArch: Add atomic/locking headers LoongArch: Add CPU definition headers LoongArch: Add build infrastructure LoongArch: Add writecombine support for drm LoongArch: Add ELF-related definitions ...
2 parents 21873bd + 8be4493 commit c6f2f3e

File tree

204 files changed

+21064
-7
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

204 files changed

+21064
-7
lines changed

‎Documentation/arch.rst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ implementation.
1313
arm/index
1414
arm64/index
1515
ia64/index
16+
loongarch/index
1617
m68k/index
1718
mips/index
1819
nios2/index

‎Documentation/loongarch/features.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
.. SPDX-License-Identifier: GPL-2.0
2+
3+
.. kernel-feat:: $srctree/Documentation/features loongarch

‎Documentation/loongarch/index.rst

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
.. SPDX-License-Identifier: GPL-2.0
2+
3+
======================
4+
LoongArch Architecture
5+
======================
6+
7+
.. toctree::
8+
:maxdepth: 2
9+
:numbered:
10+
11+
introduction
12+
irq-chip-model
13+
14+
features
15+
16+
.. only:: subproject and html
17+
18+
Indices
19+
=======
20+
21+
* :ref:`genindex`

‎Documentation/loongarch/introduction.rst

Lines changed: 387 additions & 0 deletions
Large diffs are not rendered by default.

‎Documentation/loongarch/irq-chip-model.rst

Lines changed: 156 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,156 @@
1+
.. SPDX-License-Identifier: GPL-2.0
2+
3+
=======================================
4+
IRQ chip model (hierarchy) of LoongArch
5+
=======================================
6+
7+
Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
8+
with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
9+
Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
10+
I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11+
PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12+
in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
13+
14+
CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15+
controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
16+
in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy,
17+
and there are two models of hierarchy (legacy model and extended model).
18+
19+
Legacy IRQ model
20+
================
21+
22+
In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
23+
to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
24+
interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
25+
to LIOINTC, and then CPUINTC::
26+
27+
+-----+ +---------+ +-------+
28+
| IPI | --> | CPUINTC | <-- | Timer |
29+
+-----+ +---------+ +-------+
30+
^
31+
|
32+
+---------+ +-------+
33+
| LIOINTC | <-- | UARTs |
34+
+---------+ +-------+
35+
^
36+
|
37+
+-----------+
38+
| HTVECINTC |
39+
+-----------+
40+
^ ^
41+
| |
42+
+---------+ +---------+
43+
| PCH-PIC | | PCH-MSI |
44+
+---------+ +---------+
45+
^ ^ ^
46+
| | |
47+
+---------+ +---------+ +---------+
48+
| PCH-LPC | | Devices | | Devices |
49+
+---------+ +---------+ +---------+
50+
^
51+
|
52+
+---------+
53+
| Devices |
54+
+---------+
55+
56+
Extended IRQ model
57+
==================
58+
59+
In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
60+
to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
61+
interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
62+
to CPUINTC directly::
63+
64+
+-----+ +---------+ +-------+
65+
| IPI | --> | CPUINTC | <-- | Timer |
66+
+-----+ +---------+ +-------+
67+
^ ^
68+
| |
69+
+---------+ +---------+ +-------+
70+
| EIOINTC | | LIOINTC | <-- | UARTs |
71+
+---------+ +---------+ +-------+
72+
^ ^
73+
| |
74+
+---------+ +---------+
75+
| PCH-PIC | | PCH-MSI |
76+
+---------+ +---------+
77+
^ ^ ^
78+
| | |
79+
+---------+ +---------+ +---------+
80+
| PCH-LPC | | Devices | | Devices |
81+
+---------+ +---------+ +---------+
82+
^
83+
|
84+
+---------+
85+
| Devices |
86+
+---------+
87+
88+
ACPI-related definitions
89+
========================
90+
91+
CPUINTC::
92+
93+
ACPI_MADT_TYPE_CORE_PIC;
94+
struct acpi_madt_core_pic;
95+
enum acpi_madt_core_pic_version;
96+
97+
LIOINTC::
98+
99+
ACPI_MADT_TYPE_LIO_PIC;
100+
struct acpi_madt_lio_pic;
101+
enum acpi_madt_lio_pic_version;
102+
103+
EIOINTC::
104+
105+
ACPI_MADT_TYPE_EIO_PIC;
106+
struct acpi_madt_eio_pic;
107+
enum acpi_madt_eio_pic_version;
108+
109+
HTVECINTC::
110+
111+
ACPI_MADT_TYPE_HT_PIC;
112+
struct acpi_madt_ht_pic;
113+
enum acpi_madt_ht_pic_version;
114+
115+
PCH-PIC::
116+
117+
ACPI_MADT_TYPE_BIO_PIC;
118+
struct acpi_madt_bio_pic;
119+
enum acpi_madt_bio_pic_version;
120+
121+
PCH-MSI::
122+
123+
ACPI_MADT_TYPE_MSI_PIC;
124+
struct acpi_madt_msi_pic;
125+
enum acpi_madt_msi_pic_version;
126+
127+
PCH-LPC::
128+
129+
ACPI_MADT_TYPE_LPC_PIC;
130+
struct acpi_madt_lpc_pic;
131+
enum acpi_madt_lpc_pic_version;
132+
133+
References
134+
==========
135+
136+
Documentation of Loongson-3A5000:
137+
138+
https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)
139+
140+
https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)
141+
142+
Documentation of Loongson's LS7A chipset:
143+
144+
https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)
145+
146+
https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)
147+
148+
Note: CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
149+
in Section 7.4 of "LoongArch Reference Manual, Vol 1"; LIOINTC is "Legacy I/O
150+
Interrupts" described in Section 11.1 of "Loongson 3A5000 Processor Reference
151+
Manual"; EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
152+
"Loongson 3A5000 Processor Reference Manual"; HTVECINTC is "HyperTransport
153+
Interrupts" described in Section 14.3 of "Loongson 3A5000 Processor Reference
154+
Manual"; PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
155+
"Loongson 7A1000 Bridge User Manual"; PCH-LPC is "LPC Interrupts" described in
156+
Section 24.3 of "Loongson 7A1000 Bridge User Manual".

‎Documentation/translations/zh_CN/index.rst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,7 @@ TODOList:
171171
riscv/index
172172
openrisc/index
173173
parisc/index
174+
loongarch/index
174175

175176
TODOList:
176177

‎Documentation/translations/zh_CN/loongarch/features.rst

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
.. SPDX-License-Identifier: GPL-2.0
2+
3+
.. include:: ../disclaimer-zh_CN.rst
4+
5+
:Original: Documentation/loongarch/features.rst
6+
:Translator: Huacai Chen <[email protected]>
7+
8+
.. kernel-feat:: $srctree/Documentation/features loongarch

‎Documentation/translations/zh_CN/loongarch/index.rst

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
.. SPDX-License-Identifier: GPL-2.0
2+
3+
.. include:: ../disclaimer-zh_CN.rst
4+
5+
:Original: Documentation/loongarch/index.rst
6+
:Translator: Huacai Chen <[email protected]>
7+
8+
=================
9+
LoongArch体系结构
10+
=================
11+
12+
.. toctree::
13+
:maxdepth: 2
14+
:numbered:
15+
16+
introduction
17+
irq-chip-model
18+
19+
features
20+
21+
.. only:: subproject and html
22+
23+
Indices
24+
=======
25+
26+
* :ref:`genindex`

0 commit comments

Comments
 (0)