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Merge tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.15 kernel cycle, no core changes at all this time, just driver work! New drivers: - New subdriver for Intel Keem Bay (an ARM-based SoC) - New subdriver for Qualcomm MDM9607 and SM6115 - New subdriver for ST Microelectronics STM32MP135 - New subdriver for Freescale i.MX8ULP ("Ultra Low Power") - New subdriver for Ingenic X2100 - Support for Qualcomm PMC8180, PMC8180C, SA8155p-adp PMIC GPIO - Support Samsung Exynos850 - Support Renesas RZ/G2L Enhancements: - A major refactoring of the Rockchip driver, breaking part of it out to a separate GPIO driver in drivers/gpio - Pin bias support on Renesas r8a77995 - Add SCI pins support to Ingenic JZ4755 and JZ4760 - Mediatek device tree bindings converted to YAML" * tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (53 commits) pinctrl: renesas: Add RZ/G2L pin and gpio controller driver pinctrl: samsung: Add Exynos850 SoC specific data dt-bindings: pinctrl: samsung: Add Exynos850 doc MAINTAINERS: Add maintainers for amd-pinctrl driver pinctrl: Add Intel Keem Bay pinctrl driver dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device dt-bindings: pinctrl: qcom-pmic-gpio: Remove the interrupts property dt-bindings: pinctrl: qcom-pmic-gpio: Convert qcom pmic gpio bindings to YAML dt-bindings: pinctrl: mt8195: Use real world values for drive-strength arguments dt-bindings: mediatek: convert pinctrl to yaml arm: dts: mt8183: Move pinfunc to include/dt-bindings/pinctrl arm: dts: mt8135: Move pinfunc to include/dt-bindings/pinctrl pinctrl: ingenic: Add .max_register in regmap_config pinctrl: ingenic: Fix bias config for X2000(E) pinctrl: ingenic: Fix incorrect pull up/down info pinctrl: Ingenic: Add pinctrl driver for X2100. dt-bindings: pinctrl: Add bindings for Ingenic X2100. pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760. pinctrl: Ingenic: Improve the code. ...
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‎Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml

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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX8ULP IOMUX Controller
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maintainers:
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- Jacky Bai <[email protected]>
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description:
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Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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properties:
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compatible:
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const: fsl,imx8ulp-iomuxc1
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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each entry consists of 5 integers and represents the mux and config
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setting for one pin. The first 4 integers <mux_config_reg input_reg
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mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last
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integer CONFIG is the pad setting value like pull-up on this pin. Please
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refer to i.MX8ULP Reference Manual for detailed CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
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"mux_config_reg" indicates the offset of mux register.
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- description: |
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"input_reg" indicates the offset of select input register.
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- description: |
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"mux_mode" indicates the mux value to be applied.
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- description: |
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"input_val" indicates the select input value to be applied.
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- description: |
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"pad_setting" indicates the pad configuration value to be applied.
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required:
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- fsl,pins
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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# Pinmux controller node
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- |
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iomuxc: pinctrl@298c0000 {
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compatible = "fsl,imx8ulp-iomuxc1";
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reg = <0x298c0000 0x10000>;
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pinctrl_lpuart5: lpuart5grp {
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fsl,pins =
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<0x0138 0x08F0 0x4 0x3 0x3>,
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<0x013C 0x08EC 0x4 0x3 0x3>;
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};
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};
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...

‎Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml

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pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
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and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
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the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
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pins. The X2000 contains 5 GPIO ports, PA to PE, for a total of 160 pins.
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The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO
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ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports,
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PA to PG, for a total of 224 pins.
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pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of
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160 pins. The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains
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6 GPIO ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO
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ports, PA to PG, for a total of 224 pins.
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maintainers:
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- Paul Cercueil <[email protected]>
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- ingenic,x1500-pinctrl
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- ingenic,x1830-pinctrl
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- ingenic,x2000-pinctrl
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- ingenic,x2100-pinctrl
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- items:
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- const: ingenic,jz4760b-pinctrl
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- const: ingenic,jz4760-pinctrl
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- ingenic,x1500-gpio
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- ingenic,x1830-gpio
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- ingenic,x2000-gpio
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- ingenic,x2100-gpio
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reg:
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items:

‎Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel Keem Bay pin controller Device Tree Bindings
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maintainers:
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- Lakshmi Sowjanya D <[email protected]>
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description: |
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Intel Keem Bay SoC integrates a pin controller which enables control
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of pin directions, input/output values and configuration
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for a total of 80 pins.
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properties:
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compatible:
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const: intel,keembay-pinctrl
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reg:
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maxItems: 2
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gpio-controller: true
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'#gpio-cells':
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const: 2
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ngpios:
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description: The number of GPIOs exposed.
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const: 80
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interrupts:
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description:
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Specifies the interrupt lines to be used by the controller.
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Each interrupt line is shared by upto 4 GPIO lines.
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maxItems: 8
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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patternProperties:
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'^gpio@[0-9a-f]*$':
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type: object
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description:
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Child nodes can be specified to contain pin configuration information,
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which can then be utilized by pinctrl client devices.
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The following properties are supported.
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properties:
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pins:
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description: |
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The name(s) of the pins to be configured in the child node.
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Supported pin names are "GPIO0" up to "GPIO79".
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength:
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description: IO pads drive strength in milli Ampere.
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enum: [2, 4, 8, 12]
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bias-bus-hold:
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type: boolean
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input-schmitt-enable:
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type: boolean
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slew-rate:
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description: GPIO slew rate control.
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0 - Fast(~100MHz)
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1 - Slow(~50MHz)
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enum: [0, 1]
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additionalProperties: false
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required:
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- compatible
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- reg
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- gpio-controller
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- ngpios
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- '#gpio-cells'
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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// Example 1
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gpio@0 {
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compatible = "intel,keembay-pinctrl";
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reg = <0x600b0000 0x88>,
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<0x600b0190 0x1ac>;
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gpio-controller;
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ngpios = <0x50>;
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#gpio-cells = <0x2>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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// Example 2
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gpio@1 {
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compatible = "intel,keembay-pinctrl";
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reg = <0x600c0000 0x88>,
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<0x600c0190 0x1ac>;
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gpio-controller;
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ngpios = <0x50>;
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#gpio-cells = <0x2>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};

‎Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt

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group pwm0
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- pin 11 (GPIO1-11)
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- functions pwm, gpio
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- functions pwm, led, gpio
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group pwm1
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- pin 12
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- functions pwm, gpio
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- functions pwm, led, gpio
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group pwm2
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- pin 13
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- functions pwm, gpio
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- functions pwm, led, gpio
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group pwm3
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- pin 14
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- functions pwm, gpio
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- functions pwm, led, gpio
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group pmic1
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- pin 7

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