@@ -6790,7 +6790,7 @@ create_stream_for_sink(struct drm_connector *connector,
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if (stream -> out_transfer_func .tf == TRANSFER_FUNCTION_GAMMA22 )
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tf = TRANSFER_FUNC_GAMMA_22 ;
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mod_build_vsc_infopacket (stream , & stream -> vsc_infopacket , stream -> output_color_space , tf );
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- aconnector -> psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY ;
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+ aconnector -> sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY ;
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}
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finish :
@@ -9047,7 +9047,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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* during the PSR-SU was disabled.
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*/
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if (acrtc_state -> stream -> link -> psr_settings .psr_version >= DC_PSR_VERSION_SU_1 &&
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- acrtc_attach -> dm_irq_params .allow_psr_entry &&
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+ acrtc_attach -> dm_irq_params .allow_sr_entry &&
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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!amdgpu_dm_crc_window_is_activated (acrtc_state -> base .crtc ) &&
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#endif
@@ -9282,27 +9282,27 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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}
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}
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- /* Decrement skip count when PSR is enabled and we're doing fast updates. */
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+ /* Decrement skip count when SR is enabled and we're doing fast updates. */
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if (acrtc_state -> update_type == UPDATE_TYPE_FAST &&
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acrtc_state -> stream -> link -> psr_settings .psr_feature_enabled ) {
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struct amdgpu_dm_connector * aconn =
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(struct amdgpu_dm_connector * )acrtc_state -> stream -> dm_stream_context ;
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- if (aconn -> psr_skip_count > 0 )
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- aconn -> psr_skip_count -- ;
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+ if (aconn -> sr_skip_count > 0 )
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+ aconn -> sr_skip_count -- ;
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- /* Allow PSR when skip count is 0. */
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- acrtc_attach -> dm_irq_params .allow_psr_entry = !aconn -> psr_skip_count ;
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+ /* Allow SR when skip count is 0. */
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+ acrtc_attach -> dm_irq_params .allow_sr_entry = !aconn -> sr_skip_count ;
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/*
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- * If sink supports PSR SU, there is no need to rely on
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- * a vblank event disable request to enable PSR. PSR SU
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+ * If sink supports PSR SU/Panel Replay , there is no need to rely on
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+ * a vblank event disable request to enable PSR/RP . PSR SU/RP
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* can be enabled immediately once OS demonstrates an
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* adequate number of fast atomic commits to notify KMD
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* of update events. See `vblank_control_worker()`.
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*/
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if (acrtc_state -> stream -> link -> psr_settings .psr_version >= DC_PSR_VERSION_SU_1 &&
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- acrtc_attach -> dm_irq_params .allow_psr_entry &&
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+ acrtc_attach -> dm_irq_params .allow_sr_entry &&
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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!amdgpu_dm_crc_window_is_activated (acrtc_state -> base .crtc ) &&
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#endif
@@ -9313,7 +9313,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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500000000 )
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amdgpu_dm_psr_enable (acrtc_state -> stream );
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} else {
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- acrtc_attach -> dm_irq_params .allow_psr_entry = false;
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+ acrtc_attach -> dm_irq_params .allow_sr_entry = false;
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}
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mutex_unlock (& dm -> dc_lock );
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