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* descriptor base address in the upper 8 bits.
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*/
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struct jz4780_dma_hwdesc {
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- uint32_t dcm ;
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- uint32_t dsa ;
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- uint32_t dta ;
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- uint32_t dtc ;
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+ u32 dcm ;
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+ u32 dsa ;
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+ u32 dta ;
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+ u32 dtc ;
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};
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/* Size of allocations for hardware descriptor blocks. */
@@ -122,16 +122,16 @@ struct jz4780_dma_desc {
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dma_addr_t desc_phys ;
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unsigned int count ;
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enum dma_transaction_type type ;
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- uint32_t status ;
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+ u32 status ;
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};
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struct jz4780_dma_chan {
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struct virt_dma_chan vchan ;
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unsigned int id ;
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struct dma_pool * desc_pool ;
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- uint32_t transfer_type ;
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- uint32_t transfer_shift ;
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+ u32 transfer_type ;
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+ u32 transfer_shift ;
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struct dma_slave_config config ;
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struct jz4780_dma_desc * desc ;
@@ -152,12 +152,12 @@ struct jz4780_dma_dev {
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unsigned int irq ;
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const struct jz4780_dma_soc_data * soc_data ;
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- uint32_t chan_reserved ;
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+ u32 chan_reserved ;
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struct jz4780_dma_chan chan [];
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};
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struct jz4780_dma_filter_data {
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- uint32_t transfer_type ;
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+ u32 transfer_type ;
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int channel ;
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};
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@@ -179,26 +179,26 @@ static inline struct jz4780_dma_dev *jz4780_dma_chan_parent(
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dma_device );
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}
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- static inline uint32_t jz4780_dma_chn_readl (struct jz4780_dma_dev * jzdma ,
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+ static inline u32 jz4780_dma_chn_readl (struct jz4780_dma_dev * jzdma ,
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unsigned int chn , unsigned int reg )
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{
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return readl (jzdma -> chn_base + reg + JZ_DMA_REG_CHAN (chn ));
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}
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static inline void jz4780_dma_chn_writel (struct jz4780_dma_dev * jzdma ,
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- unsigned int chn , unsigned int reg , uint32_t val )
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+ unsigned int chn , unsigned int reg , u32 val )
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{
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writel (val , jzdma -> chn_base + reg + JZ_DMA_REG_CHAN (chn ));
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}
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- static inline uint32_t jz4780_dma_ctrl_readl (struct jz4780_dma_dev * jzdma ,
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+ static inline u32 jz4780_dma_ctrl_readl (struct jz4780_dma_dev * jzdma ,
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unsigned int reg )
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{
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return readl (jzdma -> ctrl_base + reg );
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}
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static inline void jz4780_dma_ctrl_writel (struct jz4780_dma_dev * jzdma ,
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- unsigned int reg , uint32_t val )
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+ unsigned int reg , u32 val )
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{
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writel (val , jzdma -> ctrl_base + reg );
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}
@@ -260,8 +260,8 @@ static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc)
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kfree (desc );
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}
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- static uint32_t jz4780_dma_transfer_size (struct jz4780_dma_chan * jzchan ,
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- unsigned long val , uint32_t * shift )
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+ static u32 jz4780_dma_transfer_size (struct jz4780_dma_chan * jzchan ,
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+ unsigned long val , u32 * shift )
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{
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struct jz4780_dma_dev * jzdma = jz4780_dma_chan_parent (jzchan );
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int ord = ffs (val ) - 1 ;
@@ -303,7 +303,7 @@ static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
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enum dma_transfer_direction direction )
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{
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struct dma_slave_config * config = & jzchan -> config ;
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- uint32_t width , maxburst , tsz ;
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+ u32 width , maxburst , tsz ;
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if (direction == DMA_MEM_TO_DEV ) {
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desc -> dcm = JZ_DMA_DCM_SAI ;
@@ -453,7 +453,7 @@ static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy(
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{
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struct jz4780_dma_chan * jzchan = to_jz4780_dma_chan (chan );
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struct jz4780_dma_desc * desc ;
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- uint32_t tsz ;
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+ u32 tsz ;
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desc = jz4780_dma_desc_alloc (jzchan , 1 , DMA_MEMCPY );
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if (!desc )
@@ -670,7 +670,7 @@ static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
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{
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const unsigned int soc_flags = jzdma -> soc_data -> flags ;
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struct jz4780_dma_desc * desc = jzchan -> desc ;
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- uint32_t dcs ;
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+ u32 dcs ;
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bool ack = true;
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spin_lock (& jzchan -> vchan .lock );
@@ -727,7 +727,7 @@ static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
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struct jz4780_dma_dev * jzdma = data ;
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unsigned int nb_channels = jzdma -> soc_data -> nb_channels ;
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unsigned long pending ;
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- uint32_t dmac ;
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+ u32 dmac ;
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int i ;
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pending = jz4780_dma_ctrl_readl (jzdma , JZ_DMA_REG_DIRQP );
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